HDMI PHY Intel FPGA IP User Guide

Download PDF
ID 732147
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. HDMI PHY Intel® FPGA IP Quick Reference 2. HDMI PHY Overview 3. HDMI PHY Intel® FPGA IP Getting Started 4. HDMI Hardware Design Examples 5. HDMI RX PHY 6. HDMI TX PHY 7. PHY Arbiter and Transceiver Merging 8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide
2. HDMI PHY Overview x
2.1. Release Information 2.2. Device Family Support 2.3. Feature Support 2.4. Resource Utilization
3. HDMI PHY Intel® FPGA IP Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel FPGA IP Evaluation Mode
4. HDMI Hardware Design Examples x
4.1. HDMI Hardware Design Examples for Intel® Arria® 10 4.2. HDMI Hardware Design Examples for Intel® Agilex™ F-Tile
5. HDMI RX PHY x
5.1. HDMI 2.0 (Support FRL = 0) 5.2. HDMI 2.1 (Support FRL = 1)
5.1. HDMI 2.0 (Support FRL = 0) x
5.1.1. Architecture 5.1.2. Dynamic Reconfiguration 5.1.3. IP Ports 5.1.4. IP Configuration Parameters 5.1.5. RX PHY Address Map
5.2. HDMI 2.1 (Support FRL = 1) x
5.2.1. Architecture 5.2.2. Dynamic Reconfiguration 5.2.3. IP Ports 5.2.4. IP Configuration Parameters 5.2.5. RX PHY Address Map
6. HDMI TX PHY x
6.1. HDMI 2.0 (Support FRL = 0) 6.2. HDMI 2.1 (Support FRL = 1)
6.1. HDMI 2.0 (Support FRL = 0) x
6.1.1. Architecture 6.1.2. Dynamic Reconfiguration 6.1.3. IP Ports 6.1.4. IP Configuration Parameters 6.1.5. TX PHY Address Map
6.2. HDMI 2.1 (Support FRL = 1) x
6.2.1. Architecture 6.2.2. Dynamic Reconfiguration 6.2.3. IP Ports 6.2.4. IP Configuration Parameters 6.2.5. TX PHY Address Map
7. PHY Arbiter and Transceiver Merging x
7.1. PHY Arbiter IP Ports 7.2. IP Configuration Parameters 7.3. PHY Merging and Arbiter Connection
7.3. PHY Merging and Arbiter Connection x
7.3.1. RX-Only and TX-Only Use Cases 7.3.2. Single RX and TX Simple Merge 7.3.3. Complex Straddled Channels
1. HDMI PHY Intel® FPGA IP Quick Reference
2. HDMI PHY Overview
3. HDMI PHY Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI RX PHY
6. HDMI TX PHY
7. PHY Arbiter and Transceiver Merging
8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide

5.1.1. Architecture

Figure 4. HDMI RX PHY Architecture

The HDMI RX PHY performs the following main functions:

  • Allows software to switch the transceiver reference clock from the fr_clk to the rx_tmds_clk. RX PHY includes a free running fr_clk as reference clock 0 to handle the specific HDMI use case where there is no refclk to the transceiver due to the HDMI cable not plugged in (refclk to the transceiver comes from the HDMI RX connector). Without refclk transceiver input, power-up calibration takes longer to complete.
  • Reconfig Management block measures frequency of the incoming HDMI TMDS clock (rx_tmds_clk) to determine the received video pixel rate.
  • Reconfigures the RX transceivers according to the received video pixel rate.
  • Generates video clock (vid_clk) and link-speed clock (ls_clk) from rx_tmds_clk.
  • Recovers serial HDMI data and outputs parallel HDMI RX data.

Software accesses the transceiver reconfiguration registers via the av_mm_control bus and the Avalon Bridge, which directs accesses for the corresponding address range to the transceiver reconfiguration registers. The Avalon Mux must be setup accordingly via the RX_RCFG_EN bit. Refer to the RX PHY Address Map section for HDMI 2.0.

Various other registers are provided for the software (refer to the RX PHY Address Map section for HDMI 2.0). These provide various statuses and controls, and some debug information to the controlling software.

The IOPLL takes the rx_tmds_clk and generates a reference clock for the RX transceiver’s CMU or CDR PLL as well as vid_clk and ls_clk which are connected to the HDMI RX core.

Oversampling operates on the RX side in case the data received is below the 1 Gbps minimum transceiver data rate. For example, a video resolution with TMDS Bit Rates of 742.5 Mbps should configure the transceiver to operate at five times its data rate, which is 3.7125 Gb/s. The oversampling factor on the RX is set to 5 and so for data rates less than 1Gbps, the IOPLL produces a CMU or CDR reference clock of 5 x rx_tmds_clk frequency.

The frequency of ls_clk is the TMDS data rate per lane per 20. Note that when oversampling is active, the transceiver data rate is five times higher than the TMDS data rate.

The vid_clk frequency depends also on color depth:

vid_clk frequency = ls_clk / color depth ratio

Table 9.  Color Depth Ratio
Bits per Color Color Depth Ratio
8 1.0
10 1.25
12 1.5
16 2.0
Level Two Title