4G Turbo-V Intel® FPGA IP User Guide

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ID 683882
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. About the 4G Turbo-V Intel® FPGA IP 2. Getting Started with 4G Turbo-V IP 3. Designing with the 4G Turbo-V Intel® FPGA IP 4. 4G Turbo-V Intel® FPGA IP Functional Description 5. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide
1. About the 4G Turbo-V Intel® FPGA IP x
1.1. 4G Turbo-V Intel® FPGA IP Features 1.2. 4G Turbo-V Intel® FPGA IP Device Family Support 1.3. 4G Turbo-V IP Release Information 1.4. 4G Turbo-V Performance and Resource Utilization
2. Getting Started with 4G Turbo-V IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 4G Turbo-V IP Timeout Behavior
3. Designing with the 4G Turbo-V Intel® FPGA IP x
3.1. Generating a 4G Turbo-V IP 3.2. Simulating the IP with the RTL Simulator 3.3. Simulating a 4G Turbo-V IP with MATLAB 3.4. Simulating a 4G Turbo-V IP with C-Models
4. 4G Turbo-V Intel® FPGA IP Functional Description x
4.1. 4G Turbo-V Downlink Accelerator 4.2. 4G Turbo-V Uplink Accelerator 4.3. 4G Turbo-V Signals and Interfaces
4.1. 4G Turbo-V Downlink Accelerator x
4.1.1. Turbo Encoder 4.1.2. Rate Matcher 4.1.3. Input and Output Data Formats 4.1.4. Latency Calculations 4.1.5. Throughput Calculations
4.2. 4G Turbo-V Uplink Accelerator x
4.2.1. Turbo Decoder 4.2.2. Input and Output Data Formats 4.2.3. Latency Calculations 4.2.4. Throughput Calculations
4.3. 4G Turbo-V Signals and Interfaces x
4.3.1. Avalon Streaming Interfaces in DSP Intel FPGA IP
1. About the 4G Turbo-V Intel® FPGA IP
2. Getting Started with 4G Turbo-V IP
3. Designing with the 4G Turbo-V Intel® FPGA IP
4. 4G Turbo-V Intel® FPGA IP Functional Description
5. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide

4.1.3. Input and Output Data Formats

Downlink accelerator data formats.
Table 7.  Input Data FormatThe downlink accelerator takes 8 bits per clock cycle for a total of K-24 bits, when crc_enable = 1.
Input Order sink_data
7…0
0 c7 c6 c5 c4 c3 c2 c1 c0
1 c15 c14 c13 c12 c11 c10 c9 c8
… …
K/8-4 cK-25 cK-26 cK-27 cK-28 cK-29 cK-30 cK-31 cK-32
Table 8.  Input Data FormatThe downlink accelerator takes 8 bits per clock cycle for a total of K bits, when crc_enable = 0.
Input Order sink_data
7…0
0 c7 c6 c5 c4 c3 c2 c1 c0
1 c15 c14 c13 c12 c11 c10 c9 c8
… …
K/8-1 cK-1 cK-2 cK-3 cK-4 cK-5 cK-6 cK-7 cK-8
Table 9.  Ouput Data FormatsThe downlink accelerator outputs 24 bits per clock cycle for a total of E bits.
Output Order source_data
23…0
0 e23 e22 e21 … e2 e1 e0
1 e47 e46 e45 … e26 e25 e24
… …
E/24-1 eE-1 eE-2 eE-3 … eE-22 eE-23 eE-24
Table 10.  Ouput Data FormatsThe downlink accelerator outputs 24 bits per clock cycle for a total of 3K+12 bits, when rate matcher is bypassed.

Output Order

source_data
23…16 15…8 7…0
0 Z’7 Z’6 Z’5 Z’4 Z’3 Z’2 Z’1 Z’0 Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 X7 X6 X5 X4 X3 X2 X1 X0
1 Z’15 Z’14 Z’13 Z’12 Z’11 Z’10 Z’9 Z’8 Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 X15 X14 X13 X12 X11 X10 X9 X8
… … … …
K/8-1 Z’K-1 Z’K-2 Z’K-3 Z’K-4 Z’K-5 Z’K-6 Z’K-7 Z’K-8 ZK-1 ZK-2 ZK-3 ZK-4 ZK-5 ZK-6 ZK-7 ZK-8 XK-1 XK-2 XK-3 XK-4 XK-5 XK-6 XK-7 XK-8
K/8 4’bx Z’K+2 X’K+1 ZK+2 XK+1 4’bx X’K+2 Z’K XK+2 ZK 4’bx Z’K+1 X’K ZK+1 XK

The outputs of the last clock cycle are corresponding to 12 termination bits from turbo encoder, where output bits 23, 22, 21, 20, 15, 14, 13, 12, 7, 6, 5, 4 in the last clock cycle are unused (don’t care) bits.

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