Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

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ID 683814
Date 1/14/2022
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Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines x
Intel® Arria® 10 GX and GT Pin Connection Guidelines Intel® Arria® 10 SX Pin Connection Guidelines Power Supply Sharing Guidelines for Intel® Arria® 10 Devices Document Revision History for the Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
Intel® Arria® 10 GX and GT Pin Connection Guidelines x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins Partial Reconfiguration Pins 3V Compatible I/O Pins Differential I/O Pins External Memory Interface and Hard Memory PHY Pins Reference Pins Voltage Sensor Pins Supply Pins Transceiver Pins Notes to Intel® Arria® 10 GX and GT Pin Connection Guidelines
Intel® Arria® 10 SX Pin Connection Guidelines x
HPS Supply Pins HPS Dedicated I/O Bank Pins HPS Peripheral Pins Shared 3V I/O Bank Pins Notes to Intel® Arria® 10 SX Pin Connection Guidelines
Power Supply Sharing Guidelines for Intel® Arria® 10 Devices x
Example 1— Intel® Arria® 10 GX Example 2— Intel® Arria® 10 GX Example 3— Intel® Arria® 10 GX Example 4— Intel® Arria® 10 GT Example 5— Intel® Arria® 10 GT Example 6— Intel® Arria® 10 GT Example 7— Intel® Arria® 10 GT Example 8— Intel® Arria® 10 SX Example 9— Intel® Arria® 10 SX Example 10— Intel® Arria® 10 SX Example 11— Intel® Arria® 10 GX (Using the SmartVID Feature) Notes to Power Supply Sharing Guidelines
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

Optional/Dual-Purpose Configuration Pins

Note: Intel® recommends that you create a Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 3.  Optional/Dual-Purpose Configuration Pins
Pin Name Pin Functions Pin Description Connection Guidelines
DCLK Input (PS, FPP); Output (AS)

Dedicated configuration clock pin. In passive serial (PS) and fast passive parallel (FPP) configuration schemes, DCLK is used to clock configuration data from an external source into the FPGA.

In the AS configuration scheme, DCLK is an output from the FPGA that provides timing for the configuration interface.

Do not leave this pin floating. Drive this pin either high or low.
CRC_ERROR I/O, Output (open-drain)

Active high signal indicates the error detection circuit has detected errors in the configuration RAM (CRAM) bits.

Falling edge of this signal indicates the information about the error location and type are available in the error message register (EMR).

This dual-purpose pin is only used when you enable error detection in user mode.

This pin can be used as a user I/O pin.

When you use the open-drain output dedicated CRC_ERROR pin as an optional pin, connect this pin through an external 10-kΩ pull-up resistor to VCCPGM.

When you do not use the open-drain output dual-purpose CRC_ERROR pin as an optional pin, and the CRC_ERROR pin is not used as an I/O pin, connect this pin as defined in the Intel® Quartus® Prime software.

DEV_CLRn I/O, Input

Optional pin that allows you to override all clears on all device registers.

When this pin is driven low, all registers are cleared. When this pin is driven high (VCCPGM), all registers behave as programmed.

When you do not use the dual-purpose DEV_CLRn pin and when this pin is not used as an I/O pin, tie this pin to GND.
DEV_OE I/O, Input

Optional pin that allows you to override all tri-states on the device.

When this pin is driven low, all I/O pins are tri-stated. When this pin is driven high (VCCPGM), all I/O pins behave as programmed.

When you do not use the dual-purpose DEV_OE pin and when this pin is not used as an I/O pin, tie this pin to GND.
DATA0 I/O, Input Dual-purpose configuration data input pin. You can use the DATA0 pin for PS or FPP configuration scheme, or as an I/O pin after configuration is complete. When you do not use the dedicated input DATA0 pin and when this pin is not used as an I/O pin, leave this pin unconnected.
DATA[1:31] I/O, Input

Dual-purpose configuration data input pins.

Use DATA [1:7] pins for FPP x8, DATA [1:15] pins for FPP x16, and DATA [1:31] pins for FPP x32 configuration or as regular I/O pins. These pins can also be used as user I/O pins after configuration.

When you do not use the dual-purpose DATA[1:31] pins and when these pins are not used as I/O pins, leave these pins unconnected.
INIT_DONE I/O, Output (open-drain)

This is a dual-purpose pin and can be used as an I/O pin when not enabled as the INIT_DONE pin.

When you enable this pin, a transition from low to high at the pin indicates the device has entered user mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be used as a user I/O pin after configuration.

When you use the optionally open-drain output dedicated INIT_DONE pin, connect this pin to an external 10-kΩ pull-up resistor to VCCPGM.

When you use this pin in an AS or PS multi-device configuration mode, ensure you enable the INIT_DONE pin in the Intel® Quartus® Prime designs. When you do not use the dedicated INIT_DONE optionally open-drain output, and when this pin is not used as an I/O pin, connect this pin as defined in the Intel® Quartus® Prime software.

nPERST[L,R][0:1] I/O, Input

Dual-purpose fundamental reset pin that is only available when you use together with PCI Express* (PCIe*) hard IP (HIP).

When the pin is low, the transceivers are in reset. When the pin is high, the transceivers are out of reset. When you do not use this pin as the fundamental reset, you can use this pin as a user I/O pin.

Connect this pin as defined in the Intel® Quartus® Prime software. This pin is powered by 1.8V VCCIO supply and must be driven by 1.8V compatible I/O standards.

Connect the PCIe nPERST pin to a level translator to shift down the voltage from 3.3V LVTTL to 1.8V to interface with this pin. When this pin is not used for configuration purpose, you have the option to select 1.2V, 1.5V, or 1.8V compatible I/O standard. However, you must shift down the 3.3V LVTTL voltage from the PCIe nPERST pin to the selected Intel® Arria® 10 nPERST I/O standard voltage level.

Only one nPERST pin is used per PCIe HIP. The Intel® Arria® 10 components always have all four pins listed even when the specific component might only have 1 or 2 PCIe HIPs.

  • nPERSTL0 = Bottom Left PCIe HIP & CvP
  • nPERSTL1 = Top Left PCIe HIP (When available)
  • nPERSTR0 = Bottom Right PCIe HIP (When available)
  • nPERSTR1 = Top Right PCIe HIP (When available)

For maximum compatibility, always use the bottom left PCIe HIP first, as this is the only location that supports Configuration via Protocol (CvP) using the PCIe link.

AS_DATA0/ASDO Bidirectional Dedicated AS configuration pin. When using an EPCQ-L device (x1 mode), this is the ASDO pin and is used to send address and control signals between the FPGA device and the EPCQ-L device. When you do not program the device in the AS configuration mode, the ASDO pin is not used. When you do not use this pin, leave the pin unconnected.
AS_DATA[1:3] Bidirectional Dedicated AS configuration data pins. Configuration data is transported on these pins when connected to the EPCQ-L devices. When you do not use this pin, leave the pin unconnected.
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