CORDIC Intel® FPGA IP User Guide

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ID 683808
Date 1/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. CORDIC IP User Guide
1. CORDIC IP User Guide x
1.1. CORDIC IP Features 1.2. CORDIC IP Device Support 1.3. CORDIC IP Functional Description 1.4. CORDIC IP Parameters 1.5. CORDIC IP Signals 1.6. Document Revision History for the CORDIC Intel FPGA IP User Guide
1.3. CORDIC IP Functional Description x
1.3.1. SinCos Function 1.3.2. Atan2 Function 1.3.3. Vector Translate Function 1.3.4. Vector Rotate Function
1. CORDIC IP User Guide

1.6. Document Revision History for the CORDIC Intel FPGA IP User Guide

Document Version Intel® Quartus® Prime Version Changes
2024.01.16 23.2 Corrected Atan2 Function Signals output a width to w OUT= F OUT+3.
2023.07.07 23.2
  • Removed unsigned option in Vector Rotate Parameters
  • In Vector Rotate Signals table:
    • Removed the unsigned input [0,1] from x,y.

      Removed the unsigned input row for x0, y0.

      Changed signed input for x0, y0 to signed output.
2023.05.08 17.0 Initial release.

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