Arria V Avalon-ST Interface for PCIe Solutions User Guide

ID 683733
Date 1/04/2023
Public
Document Table of Contents

4.10. Transaction Layer Configuration Space Signals

Table 34.  Configuration Space Signals These signals are not available if Configuration Space Bypass mode is enabled.

Signal

Direction

Description

tl_cfg_add[6:0]

0utput

Address of the register that has been updated. This signal is an index indicating which Configuration Space register information is being driven onto tl_cfg_ctl. The indexing is defined in Multiplexed Configuration Register Information Available on tl_cfg_ctl . The index increments every 8coreclkout cycle. The index increments every 8 coreclkout cycles. The index consists of the following 2 fields:

  • [6:4] - indicates the function number whose information is being presented on tl_cfg_ctl
  • [3:0] - the tl_cfg_ctl tl_cfg_ctl multiplexor index
tl_cfg_ctl[31:0]

0utput

The signal is multiplexed and contains the contents of the Configuration Space registers. The indexing is defined in Multiplexed Configuration Register Information Available on tl_cfg_ctl .

tl_cfg_ctl_wr

0utput

Write signal. This signal toggles when tl_cfg_ctl has been updated (every 8 coreclkout cycles). The toggle edge marks where the tl_cfg_ctl data changes. You can use this edge as a reference to determine when the data is safe to sample.
tl_cfg_sts[122:0]

0utput

Configuration status bits. This information updates every coreclkout cycle. Bits[52:0] record status information for function0. Bits[62:53] record information for function1. Bits[72:63] record information for function 2, and so on. Refer to the following table for a detailed description of the status bits.
tl_cfg_sts_wr

0utput

Write signal. This signal toggles when tl_cfg_stshas been updated (every 8 core_clk cycles). The toggle marks the edge where tl_cfg_sts data changes. You can use this edge as a reference to determine when the data is safe to sample.
hpg_ctrler[4:0]

Input

The hpg_ctrler signals are only available in Root Port mode and when the Slot capability register is enabled. Refer to the Slot register and Slot capability register parameters in Table 6–9 on page 6–10. For Endpoint variations the hpg_ctrler input should be hardwired to 0s. The bits have the following meanings:

Input

  • [0]: Attention button pressed. This signal should be asserted when the attention button is pressed. If no attention button exists for the slot, this bit should be hardwired to 0, and the Attention Button Present bit (bit[0]) in the Slot capability register parameter is set to 0.

Input

  • [1]: Presence detect. This signal should be asserted when a presence detect circuit detects a presence detect change in the slot.

Input

  • [2]: Manually-operated retention latch (MRL) sensor changed. This signal should be asserted when an MRL sensor indicates that the MRL is Open. If an MRL Sensor does not exist for the slot, this bit should be hardwired to 0, and the MRL Sensor Present bit (bit[2]) in the Slot capability register parameter is set to 0.

Input

  • [3]: Power fault detected. This signal should be asserted when the power controller detects a power fault for this slot. If this slot has no power controller, this bit should be hardwired to 0, and the Power Controller Present bit (bit[1]) in the Slot capability register parameter is set to 0.

Input

  • [4]: Power controller status. This signal is used to set the command completed bit of the Slot Status register. Power controller status is equal to the power controller control signal. If this slot has no power controller, this bit should be hardwired to 0 and the Power Controller Present bit (bit[1]) in the Slot capability register is set to 0.
Table 35.  Mapping Between tl_cfg_sts and Configuration Space Registers

tl_cfg_sts

Configuration Space Register

Description

[62:59] Func1

[72:69] Func2

[82:79] Func3

[92:89] Func4

[102:99] Func5

[112:109] Func6

[122:119] Func7

Device Status Reg[3:0]

Records the following errors:

  • Bit 3: unsupported request
  • Bit 2: fatal error
  • Bit 1: non-fatal error
  • Bit 0: correctable error

[58:54] Func1

[68:64] Func2

[78:74] Func3

[88:84] Func4

[98:94] Func5

[108:104] Func6

[118:114] Func7

Link Status Reg[15:11]

Link status bits as follows:

  • Bit 15: link autonomous bandwidth status
  • Bit 14: link bandwidth management status
  • Bit 13: Data Link Layer link active - This bit is only active for Root Ports. It is 0 for Endpoints.
  • Bit 12: slot clock configuration
  • Bit 11: link training

[53] Func1

[63] Func2

[73] Func3

[83] Func4

[93] Func5

[103] Func6

[113] Func7

Secondary Status Reg[8]

6th primary command status error bit. Master data parity error.

[52:49]

Device Status Reg[3:0]

Records the following errors:

  • Bit 3: unsupported request detected
  • Bit 2: fatal error detected
  • Bit 1: non‑fatal error detected
  • Bit 0: correctable error detected

[48]

Slot Status Register[8]

Data Link Layer state changed

[47]

Slot Status Reg[4]

Command completed. (The hot plug controller completed a command.)

[46:31]

Link Status Reg[15:0]

Records the following link status information:

  • Bit 15: link autonomous bandwidth status
  • Bit 14: link bandwidth management status
  • Bit 13: Data Link Layer link active - This bit is only active for Root Ports. It is 0 for Endpoints.
  • Bit 12: Slot clock configuration
  • Bit 11: Link Training
  • Bit 10: Undefined
  • Bits[9:4]: Negotiated Link Width
  • Bits[3:0] Link Speed

[30]

Link Status 2 Reg[0]

Current de-emphasis level.

[29:25]

Status Reg[15:11]

Records the following 5 primary command status errors:

  • Bit 15: detected parity error
  • Bit 14: signaled system error
  • Bit 13: received master abort
  • Bit 12: received target abort
  • Bit 11: signalled target abort

[24]

Secondary Status Reg[8]

Master data parity error

[23:6]

Root Status Reg[17:0]

Records the following PME status information:

  • Bit 17: PME pending
  • Bit 16: PME status
  • Bits[15:0]: PME request ID[15:0]

[5:1]

Secondary Status Reg[15:11]

Records the following 5 secondary command status errors:

  • Bit 15: detected parity error
  • Bit 14: received system error
  • Bit 13: received master abort
  • Bit 12: received target abort
  • Bit 11: signalled target abort

[0]

Secondary Status Reg[8]

Master Data Parity Error