Intel® Cyclone® 10 GX FPGA Development Kit User Guide

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ID 683696
Date 8/15/2018
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing the Quartus Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Board Overview 4.2. Cyclone 10 GX FPGA 4.3. MAX 10 System Controller 4.4. FPGA Configuration 4.5. Status and User I/O Elements 4.6. Clocks 4.7. Memory 4.8. Power 4.9. Transceivers Interfaces and Communication Ports
4.5. Status and User I/O Elements x
4.5.1. Switches 4.5.2. Pushbuttons 4.5.3. LEDs
4.7. Memory x
4.7.1. EMIF with DDR3 4.7.2. QSPI Flash
4.9. Transceivers Interfaces and Communication Ports x
4.9.1. Transceiver Channels 4.9.2. PCIe Interface 4.9.3. SFP+ Interface 4.9.4. USB3.1 Type-C Interface 4.9.5. FPGA Mezzanine Card (FMC) Interface 4.9.6. 10/100/1000Base-T Ethernet Connector 4.9.7. I2C/PMBUS
5. Board Test System x
5.1. Preparing the Board 5.2. Running the Board Test System 5.3. Using the Board Test System
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The EPCQ Tab 5.3.5. The XCVR Tab 5.3.6. The FMC Tab 5.3.7. The DDR3 Tab 5.3.8. Power Monitor 5.3.9. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
B. Revision History x
B.1. Document Revision History for Intel® Cyclone® 10 GX FPGA Development Kit User Guide
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.9.5. FPGA Mezzanine Card (FMC) Interface

A FMC Connector (J7) is provided on the development kit for expansion. The FMC interface is compatible with the following daughter cards:
  • 12G SDI: Semtech RDK-12GSRD-ALTRA00 Evaluation Board
  • 8G DisplayPort: Bitec FMC DisplaPort Daughter Card
  • 6G HDMI 2.0: Bitec FMC HDMI Daughter Card
Table 17.  FMC Signals
Intel® Cyclone® 10 GX FPGA Development Kit SDI DisplayPort HDMI
Signal V57.1 Name Signal Name Pin Number SDI FMC Signal Name DisplayPort FMC Signal Name HDMI FMC Signal Name
FMC_DP_C2M_P0 DP0_C2M_P DP0_C2M_P C2 x FMC_TX_P0 GXB_TXp0
FMC_DP_C2M_N0 DP0_C2M_N DP0_C2M_N C3 x FMC_TX_N0 GXB_TXn0
FMC_DP_C2M_P1 DP1_C2M_P DP1_C2M_P A22 x FMC_TX_P1 GXB_TXp1
FMC_DP_C2M_N1 DP1_C2M_N DP1_C2M_N A23 x FMC_TX_N1 GXB_TXn1
FMC_DP_C2M_P2 DP2_C2M_P DP2_C2M_P A26 FMC_GS12181_IN+ FMC_TX_P2 GXB_TXp2
FMC_DP_C2M_N2 DP2_C2M_N DP2_C2M_N A27 FMC_GS12181_IN- FMC_TX_N2 GXB_TXn2
FMC_DP_C2M_P3 DP3_C2M_P DP3_C2M_P A30 x FMC_TX_P3 GXB_TXp3
FMC_DP_C2M_N3 DP3_C2M_N DP3_C2M_N A31 X FMC_TX_N3 GXB_TXn3
FMC_DP_C2M_P4 DP4_C2M_P DP4_C2M_P A34 x x x
FMC_DP_C2M_N4 DP4_C2M_N DP4_C2M_N A35 x x x
X DP5_C2M_P DP5_C2M_P A38 x x x
X DP5_C2M_N DP5_C2M_N A39 x x x
X DP6_C2M_P DP6_C2M_P B36 x x x
X DP6_C2M_N DP6_C2M_N B37 x x x
X DP7_C2M_P DP7_C2M_P B32 x x x
X DP7_C2M_N DP7_C2M_N B33 x x x
X DP8_C2M_P DP8_C2M_P B28 x x x
X DP8_C2M_N DP8_C2M_N B29 x x x
X DP9_C2M_P DP9_C2M_P B24 x x x
X DP9_C2M_N DP9_C2M_N B25 x x x
FMC_DP_M2C_P0 DP0_M2C_P DP0_M2C_P C6 x FMC_RX_P0 GXB_RXp0
FMC_DP_M2C_N0 DP0_M2C_N DP0_M2C_N C7 x FMC_RX_N0 GXB_RXn0
FMC_DP_M2C_P1 DP1_M2C_P DP1_M2C_P A2 x FMC_RX_P1 GXB_RXp1
FMC_DP_M2C_N1 DP1_M2C_N DP1_M2C_N A3 x FMC_RX_N1 GXB_RXn1
FMC_DP_M2C_P2 DP2_M2C_P DP2_M2C_P A6 FMC_GS12141_OUT+ FMC_RX_P2 GXB_RXp2
FMC_DP_M2C_N2 DP2_M2C_N DP2_M2C_N A7 FMC_GS12141_OUT- FMC_RX_N2 GXB_RXn2
FMC_DP_M2C_P3 DP3_M2C_P DP3_M2C_P A10 x FMC_RX_P3 x
FMC_DP_M2C_N3 DP3_M2C_N DP3_M2C_N A11 x FMC_RX_N3 x
FMC_DP_M2C_P4 DP4_M2C_P DP4_M2C_P A14 x x x
FMC_DP_M2C_N4 DP4_M2C_N DP4_M2C_N A15 x x x
X DP5_M2C_P DP5_M2C_P A18 x x x
X DP5_M2C_N DP5_M2C_N A19 x x x
X DP6_M2C_P DP6_M2C_P B16 x x x
X DP6_M2C_N DP6_M2C_N B17 x x x
X DP7_M2C_P DP7_M2C_P B12 x x x
X DP7_M2C_N DP7_M2C_N B13 x x x
X DP8_M2C_P DP8_M2C_P B8 x x x
X DP8_M2C_N DP8_M2C_N B9 x x x
X DP9_M2C_P DP9_M2C_P B4 x x x
X DP9_M2C_N DP9_M2C_N B5 x x x
FMC_GBTCLK_M2C_P0 GBTCLK0_M2C_P GTBCLK0_M2C_P D4 CLK_297MHz+(AC) CLK_135_N(DC) DVI_RX_CLKn(AC)
FMC_GBTCLK_M2C_N0 GBTCLK0_M2C_N GTBCLK0_M2C_N D5 CLK_297MHz-(AC) CLK_135_P(DC) DVI_RX_CLKp(AC)
X GBTCLK1_M2C_P GTBCLK1_M2C_P B20 x x x
X GBTCLK1_M2C_N GTBCLK1_M2C_N B21 x x x
LA Bank  
FMC_LA_CC_P0 LA00_P_CC LA_RX_CLK_P G6 x x x
FMC_LA_CC_N0 LA00_N_CC LA_RX_CLK_N G7 x x x
FMC_LA_CC_P1 LA01_P_CC LA_TX_CLK_P D8 x x x
FMC_LA_CC_N1 LA01_N_CC LA_TX_CLK_N D9 x x x
FMC_LA_TXP0 LA02_P LA_TX_P0 H7 FMC_GS12141_GPIO0 x x
FMC_LA_TXN0 LA02_N LA_TX_N0 H8 x x x
FMC_LA_RXP0 LA03_P LA_RX_P0 G9 x x x
FMC_LA_RXN0 LA03_N LA_RX_N0 G10 x x x
FMC_LA_TXP1 LA04_P LA_TX_P1 H10 FMC_GS12141_GPIO2 x x
FMC_LA_TXN1 LA04_N LA_TX_N1 H11 FMC_GS12141_GPIO3 x x
FMC_LA_TXP2 LA05_P LA_TX_P2 D11 x x x
FMC_LA_TXN2 LA05_N LA_TX_N2 D12 x x x
FMC_LA_RXP1 LA06_P LA_RX_P1 C10 x x x
FMC_LA_RXN1 LA06_N LA_RX_N1 C11 x x x
FMC_LA_TXP3 LA07_P LA_TX_P3 H13 FMC_GS12181_GPIO0 x x
FMC_LA_TXN3 LA07_N LA_TX_N3 H14 FMC_GS12181_GPIO1 x x
FMC_LA_RXP2 LA08_P LA_RX_P2 G12 x x x
FMC_LA_RXN2 LA08_N LA_RX_N2 G13 FMC_LMH1981_HSYNCn x x
FMC_LA_TXP4 LA09_P LA_TX_P4 D14 x x x
FMC_LA_TXN4 LA09_N LA_TX_N4 D15 x x x
FMC_LA_RXP3 LA10_P LA_RX_P3 C14 x x x
FMC_LA_RXN3 LA10_N LA_RX_N3 C15 x x x
FMC_LA_TXP5 LA11_P LA_TX_P5 H16 FMC_GS12181_GPIO2 x x
FMC_LA_TXN5 LA11_N LA_TX_N5 H17 FMC_GS12181_GPIO3 x x
FMC_LA_RXP4 LA12_P LA_RX_P4 G15 FMC_LMH1981_VSYNCn x x
FMC_LA_RXN4 LA12_N LA_RX_N4 G16 FMC_LMH1981_VIDEO_FMT x x
FMC_LA_TXP6 LA13_P LA_TX_P6 D17 x x x
FMC_LA_TXN6 LA13_N LA_TX_N6 D18 x x x
FMC_LA_RXP5 LA14_P LA_RX_P5 C18 x x x
FMC_LA_RXN5 LA14_N LA_RX_N5 C19 x x x
FMC_LA_TXP7 LA15_P LA_TX_P7 H19 x x x
FMC_LA_TXN7 LA15_N LA_TX_N7 H20 FMC_LMH1983_NO_REF x x
FMC_LA_RXP6 LA16_P LA_RX_P6 G18 FMC_LMH1981_FLD2n RX_HDP_FMC x
FMC_LA_RXN6 LA16_N LA_RX_N6 G19 x AUX_RX_DRV_OUT_FMC x
FMC_LA_TXP8 LA17_P_CC LA_TX_P8 D20 x x x
FMC_LA_TXN8 LA17_N_CC LA_TX_N8 D21 x x x
FMC_LA_RXP7 LA18_P_CC LA_RX_P7 C22 x x x
FMC_LA_RXN7 LA18_N_CC LA_RX_N7 C23 x x x
FMC_LA_TXP9 LA19_P LA_TX_P9 H22 FMC_LMH1983_NO_ALIGN AUX_RX_DRV_OE_FMC x
FMC_LA_TXN9 LA19_N LA_TX_N9 H23 FMC_LMH1983_NO_LOCK AUX_RX_DRV_IN_FMC x
FMC_LA_RXP8 LA20_P LA_RX_P8 G21 FPGA_STATUS1 TX_SCL_FMC DVI_RX_HPD_N
FMC_LA_RXN8 LA20_N LA_RX_N8 G22 x RX_SENSE_N_INV_FMC DVI_RX_SDA
FMC_LA_TXP10 LA21_P LA_TX_P10 H25 FMC_GSPI_SCLK RX_SENSE_P_INV_FMC DVI_RX_SCL
FMC_LA_TXN10 LA21_N LA_TX_N10 H26 FMC_GSPI_SDIN TX_SDA_FMC DVI_RX_CEC_IN_N
FMC_LA_RXP9 LA22_P LA_RX_P9 G24 GSPI_OEn x DVI_RX_5V_N
FMC_LA_RXN9 LA22_N LA_RX_N9 G25 FMC_GSPI_OEn TX_HPD_INV_FMC SCL
FMC_LA_TXP11 LA23_P LA_TX_P11 D23 x x SDA
FMC_LA_TXN11 LA23_N LA_TX_N11 D24 x x DVI_RX_CEC_OUT_N
FMC_LA_TXP12 LA24_P LA_TX_P12 H28 FMC_LMH1983_INIT AUX_TX_DRV_IN_FMC DVI_TX_HPD_N
FMC_LA_TXN12 LA24_N LA_TX_N12 H29 FMC_FPGA_FLDn TX_CAD_INV_FMC DVI_TX_SDA
FMC_LA_RXP10 LA25_P LA_RX_P10 G27 CLK_RATE_SEL(PU 3.3V) AUX_TX_DRV_OUT_FMC DVI_TX_SCL
FMC_LA_RXN10 LA25_N LA_RX_N10 G28 tp AUX_TX_DRV_OE_FMC DVI_TX_CEC_IN_N
FMC_LA_TXP13 LA26_P LA_TX_P13 D26 x x DVI_TX_CEC_OUT_N
FMC_LA_TXN13 LA26_N LA_TX_N13 D27 x x x
FMC_LA_RXP11 LA27_P LA_RX_P11 C26 x x x
FMC_LA_RXN11 LA27_N LA_RX_N11 C27 x TX_CAD_FPGA x
FMC_LA_TXP14 LA28_P LA_TX_P14 H31 FMC_FPGA_VSYNCn HDCP_SCL x
FMC_LA_TXN14 LA28_N LA_TX_N14 H32 FMC_FPGA_HSYNCn HDCP_SDA x
FMC_LA_RXP12 LA29_P LA_RX_P12 G30 tp x x
FMC_LA_RXN12 LA29_N LA_RX_N12 G31 x x x
FMC_LA_TXP15 LA30_P LA_TX_P15 H34 LMK03328_PDN(PU 3.3V) x x
FMC_LA_TXN15 LA30_N LA_TX_N15 H35 FMC_GSPI_CS_GS12181 x x
FMC_LA_RXP13 LA31_P LA_RX_P13 G33 x x x
FMC_LA_RXN13 LA31_N LA_RX_N13 G34 x x x
FMC_LA_TXP16 LA32_P LA_TX_P16 H37 FMC_GSPI_CS_GS12141 x x
FMC_LA_TXN16 LA32_N LA_TX_N16 H38 FMC_GSPI_SDOUT x x
FMC_LA_RXP14 LA33_P LA_RX_P14 G36 x x x
FMC_LA_RXN14 LA33_N LA_RX_N14 G37 x x x
Miscellaneous Signals  
FMCA_CLK_M2C_P0 CLK0_M2C_P CLK_M2C_P0 H4 FMC_AUDIO_CLK+ x x
FMCA_CLK_M2C_N0 CLK0_M2C_N CLK_M2C_N0 H5 FMC_AUDIO_CLK- x x
FMCA_CLK_M2C_P1 CLK1_M2C_P CLK_M2C_P1 G2 x x x
FMCA_CLK_M2C_N1 CLK1_M2C_N CLK_M2C_N1 G3 x x x
FMC_PRSNT PRSNT_M2C_L PRSNTN_M2C_L H2 x GND GND
FMC_SCL SCL SCL C30 FMC_I2C_SCL x x
FMC_SDA SDA SDA C31 FMC_I2C_SDA x x
FMC_TMS TMS JTAG_TMS D33 x x x
FMC_TDO TDO JTAG_TDO D31 x loopback Loopback
FMC_TDI TDI JTAG_TDI D30 x
FMC_TCK TCK JTAG_TCK D29 x x x
Level Two Title