You can load the configuration data for Altera devices using an active, passive, or JTAG configuration scheme. When using an active configuration scheme with a serial configuration (EPCS) or quad-serial configuration (EPCQ) device, the target FPGA generates the control and synchronization signals. When both devices are ready to begin configuration, the EPCS or EPCQ device sends data to the FPGA.
When you use any passive configuration scheme, the Altera device is incorporated into a system with an Altera configuration device or an intelligent host, such as a microprocessor, that controls the configuration process. The configuration device or host supplies configuration data from a storage device such as a configuration device, a hard disk, RAM, or other system memory. When you use passive configuration scheme, you can change the target device’s functionality while the system is in operation by reconfiguring it.
Altera devices support a number of configuration schemes. After you have decided on the appropriate configuration scheme for your system, you need to drive the dedicated mode select control pins, MSEL, of the FPGA to set the configuration mode.
Note: For more information about how to set the MSEL pins for your target device, refer to the configuration chapter in the appropriate device handbook.
Active Serial Configuration
You can perform an active serial (AS) configuration using EPCS or EPCQ devices. During AS configuration, the FPGA device is the master and the EPCS or EPCQ device is the slave. Configuration data is transferred one bit per clock cycle.
Passive Serial Configuration
You can perform a passive serial (PS) configuration using an Altera download cable, an Altera configuration device, or an intelligent host, such as a microprocessor. During PS configuration, configuration data is transferred from a storage device, such as a configuration device or flash memory, to the FPGA on the DATA0 pin. This configuration data is latched into the FPGA on the rising edge of DCLK. Configuration data is transferred one bit per clock cycle.
Fast Passive Parallel Configuration
You can perform a fast passive parallel (FPP) configuration using an Altera configuration device or an intelligent host, such as a microprocessor. During FPP configuration, configuration data is transferred from a storage device, such as a configuration device or flash memory, to the FPGA on the DATA[7..0] pins. This configuration data is latched into the FPGA on the rising edge of DCLK. Configuration data is transferred one byte per clock cycle.
JTAG Configuration
You can perform a JTAG configuration using an Altera download cable or an intelligent host, such as a microprocessor. JTAG configuration uses the IEEE Std 1 149.1 JTAG interface pins and supports the Jam™ Standard Test and Programming Language (STAPL) standard.