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1. Datasheet
2. Intel Stratix 10 LL 40GbE IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Intel® Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Intel Stratix 10 LL 40GbE IP Core and Low Latency 40GbE IP Core That Targets an Arria 10 Device
12. Document Revision History for Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Intel Stratix 10 LL 40GbE IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Intel Stratix 10 LL 40GbE IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
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3.5.2. Adding the Transceiver PLL
Intel Stratix 10 LL 40GbE IP cores require an external PLL to drive the TX transceiver serial clock, in order to compile and to function correctly in hardware. In many cases, the same PLL can be shared with other transceivers in your design.
Figure 4. PLL Configuration ExampleThe TX transceiver PLL is instantiated with an Intel® FPGA ATX PLL IP core. The TX transceiver PLL must always be instantiated outside the Intel Stratix 10 LL 40GbE IP core.
You can use the IP Catalog to create a transceiver PLL.
- Select Stratix 10 Transceiver ATX PLL.
- In the parameter editor, set the following parameter values:
- PLL output frequency to 5156.25 MHz. The transceiver performs dual edge clocking, using both the rising and falling edges of the input clock from the PLL. Therefore, this PLL output frequency setting supports a 10.3125 Gbps data rate through the transceiver.
- PLL integer reference clock frequency to 644.53125 MHz.
You must connect the tx_serial_clk input pin of the Intel Stratix 10 LL 40GbE IP core PHY link to the output port of the ATX PLL.