AN 114: Board Design Guidelines for Intel Programmable Device Packages

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ID 683481
Date 5/27/2022
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Document Table of Contents
Document Table of Contents x
1. AN 114: Board Design Guidelines for Intel® Programmable Device Packages
1. AN 114: Board Design Guidelines for Intel® Programmable Device Packages x
1.1. Overview of BGA Packages 1.2. PCB Layout Terminology 1.3. PCB Layout for High-Density BGA Packages 1.4. Document Revision History for AN 114: Board Design Guidelines for Intel® Programmable Device Packages
1.2. PCB Layout Terminology x
1.2.1. Escape Routing 1.2.2. Multi-Layer PCBs 1.2.3. Vias 1.2.4. Via Capture Pad 1.2.5. Surface Land Pad 1.2.6. Stringer
1.2.5. Surface Land Pad x
1.2.5.1. Non Solder Mask Defined Pad 1.2.5.2. Solder Mask Defined Pad
1.3. PCB Layout for High-Density BGA Packages x
1.3.1. Surface Land Pad Dimension 1.3.2. Via Capture Pad Layout and Dimension 1.3.3. Signal Line Space and Trace Width 1.3.4. Number of PCB Layers
1.3.4. Number of PCB Layers x
1.3.4.1. Sample PCB Layout for 1.00-mm Flip-Chip BGA and 0.80-mm UBGA (BT Substrate) 1.3.4.2. Sample PCB Routing Scheme on 6 Layers for 0.5-mm 484-pin MBGA 1.3.4.3. Sample PCB Routing Scheme on 3 Layers for 0.5-mm 383-pin MBGA 1.3.4.4. Sample PCB Routing Scheme on 2 Layers for 0.5-mm 301-pin MBGA 1.3.4.5. Sample PCB Routing Scheme on 2 Layers for 0.5-mm 153-pin MBGA 1.3.4.6. Sample PCB Routing Scheme on 4 Layers for 0.5-mm 144-pin MBGA 1.3.4.7. Sample PCB Routing Scheme on 2 Layers for 0.5-mm 256-pin and 100-pin MBGAs 1.3.4.8. Sample PCB Routing Scheme on 4 Layers for 0.4-mm 81-pin VBGA (also known as WLCSP) 1.3.4.9. Sample PCB Routing Scheme on 2 Layers for 0.5-mm 68-pin MBGA 1.3.4.10. Sample PCB Routing Scheme on 2 Layers for 0.4-mm 36-pin VBGA (also known as WLCSP) 1.3.4.11. Sample PCB Routing Scheme on 3 Layers for 0.8-mm 324-pin UBGA 1.3.4.12. Sample PCB Routing Scheme on 3 Layers for 0.8-mm 169-pin UBGA
1. AN 114: Board Design Guidelines for Intel® Programmable Device Packages

1.3.1. Surface Land Pad Dimension

Intel® has done extensive modeling simulation and experimental studies to determine the optimum land pad design on the PCB to provide the longest solder joint fatigue life. The results of these studies show that a pad design that provides a balanced stress on the solder joint provides the best solder joint reliability. If SMD pads are used on the PCB, the surface land pads should be the same size as the BGA pad to provide a balanced stress on solder joints. If non-solder mask defined pads are used on the PCB, the land pads should be approximately 15% smaller than the BGA pad size to achieve a balanced stress on solder joints.

Figure 5. BGA Pad Dimensions

The following table lists the recommended pad sizes for SMD and NSMD land patterns. You should use NSMD pads for high-density board layouts because the smaller pad sizes allow for more space between vias and trace routing.

Table 3.  Recommended Pad Sizes for SMD and NSMD Pads
BGA Pad Pitch BGA Pad Opening (A) (mm) (Typical) Recommended SMD Pad Size (mm) Recommended NSMD Pad Size (mm) 1
1.27 mm (Plastic Ball Grid Array (PBGA)) 0.60 0.60 0.51
1.27 mm (Super Ball Grid Array (SBGA)) 0.60 0.60 0.51
1.27 mm (Tape Ball Grid Array (TBGA)) 0.60 0.60 0.51
1.27 mm (flip-chip) 2 0.65 0.65 0.55
1.00 mm (wirebond) 2 0.45 0.45 0.38
1.00 mm (flip-chip) 2, 3 0.55 0.55 0.47
1.00 mm (flip-chip) 2 APEX 20KE 0.60 0.60 0.51
0.80 mm UBGA (wirebond) 0.40 0.40 0.34
0.80 mm UBGA (EPC16U88) 0.40 0.40 0.34
0.80 mm UBGA (flip-chip) 0.425 0.425 0.36
0.80 mm UBGA (flip-chip) 0.45 0.45 0.38
0.50 mm MBGA 0.30 0.27 0.26
Note: For more information about Intel® Stratix® 10 packages and beyond, refer to the respective individual Manufacturing Advantage Services (MAS) Guidelines document.

The following table lists the PCB design guidelines for VBGA (also known as WLCSP) 0.4-mm ball pitch.

Table 4.  Recommended Pad Sizes for VBGA (also known as WLCSP)
BGA Pad Pitch PCB Cu Pad Size NSMD (mm) Solder Mask Opening NSMD (mm) PCB Cu Pad Size SMD (mm) Solder Mask Opening SMD (mm)
0.4 mm VBGA (also known as WLCSP) 0.22 0.32 0.32 0.22

The following figures show the via and routing space available for 1.00-mm, 0.80-mm, and 0.50-mm pitch packages when using NSMD land pads.

Figure 6. Via and Routing Space Available for 1.00-mm Flip-Chip BGA NSMD Land PadsThis is not applicable for Intel® Stratix® 10 devices.
Figure 7. Via and Routing Space Available for 0.80-mm UBGA (BT Substrate) NSMD Land Pads
Figure 8. Via and Routing Space Available for 0.50-mm MBGA NSMD Land Pads
Related Information
1 Stencil opening recommendation— Intel® recommends you to use the NSMD Pad Size as the minimum stencil opening and should not go more than the SMD Pad Size for each of the BGA Package based on this table.
2 Fineline BGA packages that use flip-chip technology are marked "Thermally Enhanced FineLine BGA" and wirebond packages are marked "Non-Thermally Enhanced FineLine BGA" in the Intel® Device Package Information Datasheet.
3 This is not applicable for Intel® Stratix® 10 devices.
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