Arria® V Device Overview

Download PDF
ID 683440
Date 11/20/2020
Public
Document Table of Contents
Document Table of Contents x
1. Arria V Device Overview
1. Arria V Device Overview x
1.1. Key Advantages of Arria® V Devices 1.2. Summary of Arria® V Features 1.3. Arria® V Device Variants and Packages 1.4. I/O Vertical Migration for Arria® V Devices 1.5. Adaptive Logic Module 1.6. Variable-Precision DSP Block 1.7. Embedded Memory Blocks 1.8. Clock Networks and PLL Clock Sources 1.9. FPGA General Purpose I/O 1.10. PCIe* Gen1, Gen2, and Gen 3 Hard IP 1.11. External Memory Interface 1.12. Low-Power Serial Transceivers 1.13. SoC with HPS 1.14. Dynamic Reconfiguration 1.15. Enhanced Configuration and Configuration via Protocol 1.16. Power Management 1.17. Document Revision History
1.3. Arria® V Device Variants and Packages x
1.3.1. Arria V GX 1.3.2. Arria V GT 1.3.3. Arria V GZ 1.3.4. Arria V SX 1.3.5. Arria V ST
1.3.1. Arria V GX x
1.3.1.1. Available Options 1.3.1.2. Maximum Resources 1.3.1.3. Package Plan
1.3.2. Arria V GT x
1.3.2.1. Available Options 1.3.2.2. Maximum Resources 1.3.2.3. Package Plan
1.3.3. Arria V GZ x
1.3.3.1. Available Options 1.3.3.2. Maximum Resources 1.3.3.3. Package Plan
1.3.4. Arria V SX x
1.3.4.1. Available Options 1.3.4.2. Maximum Resources 1.3.4.3. Package Plan
1.3.5. Arria V ST x
1.3.5.1. Available Options 1.3.5.2. Maximum Resources 1.3.5.3. Package Plan
1.7. Embedded Memory Blocks x
1.7.1. Types of Embedded Memory 1.7.2. Embedded Memory Capacity in Arria V Devices 1.7.3. Embedded Memory Configurations
1.11. External Memory Interface x
1.11.1. Hard and Soft Memory Controllers 1.11.2. External Memory Performance 1.11.3. HPS External Memory Performance
1.12. Low-Power Serial Transceivers x
1.12.1. Transceiver Channels 1.12.2. PMA Features 1.12.3. PCS Features
1.13. SoC with HPS x
1.13.1. HPS Features 1.13.2. FPGA Configuration and Processor Booting 1.13.3. Hardware and Software Development
1.13.1. HPS Features x
1.13.1.1. System Peripherals and Debug Access Port 1.13.1.2. HPS–FPGA AXI Bridges 1.13.1.3. HPS SDRAM Controller Subsystem
1.14. Dynamic Reconfiguration x
1.14.1. Dynamic Reconfiguration
1. Arria V Device Overview

1.3.1.2. Maximum Resources

Table 4.  Maximum Resource Counts for Arria V GX Devices
Resource Member Code
A1 A3 A5 A7 B1 B3 B5 B7
Logic Elements (LE) (K) 75 156 190 242 300 362 420 504
ALM 28,302 58,900 71,698 91,680 113,208 136,880 158,491 190,240
Register 113,208 235,600 286,792 366,720 452,832 547,520 633,964 760,960
Memory (Kb) M10K 8,000 10,510 11,800 13,660 15,100 17,260 20,540 24,140
MLAB 463 961 1,173 1,448 1,852 2,098 2,532 2,906
Variable-precision DSP Block 240 396 600 800 920 1,045 1,092 1,156
18 x 18 Multiplier 480 792 1,200 1,600 1,840 2,090 2,184 2,312
PLL 10 10 12 12 12 12 16 16
6 Gbps Transceiver 9 9 24 24 24 24 36 36
GPIO3 416 416 544 544 704 704 704 704
LVDS Transmitter 67 67 120 120 160 160 160 160
Receiver 80 80 136 136 176 176 176 176
PCIe Hard IP Block 1 1 2 2 2 2 2 2
Hard Memory Controller 2 2 4 4 4 4 4 4
Related Information
3 The number of GPIOs does not include transceiver I/Os. In the Intel® Quartus® Prime software, the number of user I/Os includes transceiver I/Os.
Level Two Title