Intel® FPGA Streaming Video Protocol Specification

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ID 683397
Date 4/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Intel FPGA Streaming Video Protocol 2. Intel FPGA Streaming Video Protocol Description 3. Intel FPGA Streaming Video Protocol Rules 4. Intel FPGA Streaming Video Full-Raster Protocol 5. Document Revision History for Intel FPGA Streaming Video Protocol Specification
1. About the Intel FPGA Streaming Video Protocol x
1.1. Protocol Signals 1.2. Data Exchange
2. Intel FPGA Streaming Video Protocol Description x
2.1. Metapackets (Full Variants) 2.2. Video Packets
2.1. Metapackets (Full Variants) x
2.1.1. Image Information Packets 2.1.2. End-of-Field Packets 2.1.3. Auxiliary Control Packets
2.1.3. Auxiliary Control Packets x
2.1.3.1. Timestamp Packets 2.1.3.2. Register Update Packets 2.1.3.3. Commit Packets 2.1.3.4. User-defined Auxiliary Control Packets
2.2. Video Packets x
2.2.1. TDATA Pixel Packing 2.2.2. RGB Pixel Packing 2.2.3. YCbCr 444 Pixel Packing 2.2.4. YCbCr 422 Pixel Packing 2.2.5. YCbCr 420 Pixel Packing 2.2.6. Four-Channel Video Pixel Packing 2.2.7. Packing with Multiple Pixels in Parallel 2.2.8. Multiple Pixels in Parallel and Empty Pixels 2.2.9. YCbCr 422 Video with Multiple Pixels in Parallel 2.2.10. Packing RGB444 onto an RGB888 Interface 2.2.11. Packing with Less than 8 bits per Symbol Natively 2.2.12. Interlaced Fields
3. Intel FPGA Streaming Video Protocol Rules x
3.1. Rules for Packets 3.2. Rules for IPs
3.1. Rules for Packets x
3.1.1. Auxiliary Control Packet Rules
4. Intel FPGA Streaming Video Full-Raster Protocol x
4.1. Full-Raster Frame Structure 4.2. Full-Raster Start of Frame 4.3. Full-Raster TDATA Signal Layout 4.4. Full-Raster TREADY Signal 4.5. Full-Raster I/O Signals
4.4. Full-Raster TREADY Signal x
4.4.1. Full-Raster TREADY Handshake Process 4.4.2. Optional TREADY Signal: Receiver Interface 4.4.3. Optional TREADY Signal: Transmitter Interface 4.4.4. Optional Backpressure 4.4.5. Synchronous Pixel Clock Rates I/O Interfaces 4.4.6. Asynchronous Pixel Clock Rates I/O Interfaces
1. About the Intel FPGA Streaming Video Protocol
2. Intel FPGA Streaming Video Protocol Description
3. Intel FPGA Streaming Video Protocol Rules
4. Intel FPGA Streaming Video Full-Raster Protocol
5. Document Revision History for Intel FPGA Streaming Video Protocol Specification

4.1. Full-Raster Frame Structure

Generally, video timing parameters are based on two concepts: blank timing, and sync timing. Each connectivity protocol uses one of these methods to define a full-raster video frame, e.g., SDI uses blank timing and HDMI uses sync timing.

For sync-timing systems you can have:

  • Hsync – horizontal synchronization pulse
  • Vsync – vertical synchronization pulse

For blank-timing systems you can have:

  • Hblank – horizontal blanking interval
  • Vblank – vertical blanking interval

Several video technical organizations, such as the Video Electronics Standard Association (VESA), and the Consumer Electronics Association (CEA), define full-raster video timing parameters. For example, the selected video standard (e.g., SMPTE 424, CEA-861-D and VESA) or custom timing parameters programmed in the host interface define the width and timing of the Hsync, Hblank, Vsync and Vblank signals. The full-raster protocol adheres to the industry norm.

Usually, the active video data is geometrically in between the horizontal and vertical blanking areas. Both vertical and horizontal blanking areas are in four distinctive groups:

  • Front porch
  • Sync pulse
  • Back porch
  • Active video

The figures superimpose full-raster streams on top of a video frame raster, The figures show where the IP injects full raster timing information (FRn), ancillary (An) data (Pn) and active video data into the payload of the TDATA bus.

Figure 45. Timing for a Progressive Video ImageThe figure shows an example of a progressive video. The vertical dashed red line indicates the end of the video line. TLAST is asserted here.
Figure 46. Timing for an Interlaced ImageThe figure shows an example of a interlaced video. The vertical dashed red line indicates the end of the video line. TLAST is asserted here.
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