Intel® Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 12/29/2023
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Document Table of Contents x
Intel® Stratix® 10 Device Family Pin Connection Guidelines
Intel® Stratix® 10 Device Family Pin Connection Guidelines x
Intel® Stratix® 10 Core Pins Intel® Stratix® 10 High Bandwidth Memory (HBM) Pins H-Tile and L-Tile Pins Intel® Stratix® 10 E-Tile Pins Intel® Stratix® 10 P-Tile Pins Intel® Stratix® 10 Hard Processor System (HPS) Pins Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices Document Revision History for the Intel® Stratix® 10 Device Family Pin Connection Guidelines
Intel® Stratix® 10 Core Pins x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins 3V Compatible I/O Pins 3.3V I/O Pins Differential I/O Pins External Memory Interface Pins Voltage Sensor Pins Temperature Sensor Pins Reference Pins No Connect and DNU Pins Power Supply Pins Secure Device Manager (SDM) Pins Secure Device Manager (SDM) Optional Signal Pins Notes to Intel® Stratix® 10 Core Pins
Intel® Stratix® 10 High Bandwidth Memory (HBM) Pins x
UIB and eSRAM Pins Intel® Stratix® 10 HBM Power Supply Pins Notes to Intel® Stratix® 10 HBM Pins
H-Tile and L-Tile Pins x
H-Tile and L-Tile Pins
Intel® Stratix® 10 E-Tile Pins x
Intel® Stratix® 10 E-Tile Pins Notes to Intel® Stratix® 10 E-Tile Pins
Intel® Stratix® 10 P-Tile Pins x
Intel® Stratix® 10 P-Tile Power Supply Pins Intel® Stratix® 10 P-Tile Transceiver Pins
Intel® Stratix® 10 Hard Processor System (HPS) Pins x
HPS Supply Pins HPS Oscillator Clock Input Pin HPS JTAG Pins HPS GPIO Pins HPS SDMMC Pins HPS NAND Pins HPS USB Pins HPS EMAC Pins HPS I2C_EMAC and MDIO Pins HPS I2C Pins HPS SPI Pins HPS UART Pins HPS Trace Pins Notes to Intel® Stratix® 10 HPS Pins
Power Supply Sharing Guidelines for Intel® Stratix® 10 Devices x
Example 1— Intel® Stratix® 10 GX Example 2— Intel® Stratix® 10 GX Example 3— Intel® Stratix® 10 GX (only for the HF35 Package) Example 4— Intel® Stratix® 10 GX (only for the HF35 Package) Example 5— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) Example 6— Intel® Stratix® 10 SX (–2L and –3X parts) Example 7— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) Example 8— Intel® Stratix® 10 SX (–2L and –3X parts) Example 9— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 10— Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 11— Intel® Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 12— Intel® Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 13— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) Example 14— Intel® Stratix® 10 MX (–1V, –2V, and –3V parts) Example 15— Intel® Stratix® 10 MX (E-Tile) Example 16— Intel® Stratix® 10 TX (–1V, –2V, and –3V parts) Example 17— Intel® Stratix® 10 TX (–2L and –3X parts) Example 18— Intel® Stratix® 10 DX (–1V, –2V, and –3V parts) Example 19— Intel® Stratix® 10 GX 10M Example 20— Intel® Stratix® 10 GX 10M
Intel® Stratix® 10 Device Family Pin Connection Guidelines

Example 15— Intel® Stratix® 10 MX (E-Tile)

Table 49.  Power Supply Sharing Guidelines for Intel® Stratix® 10 MX (E-Tile) with L/H-Tile Transceiver Data Rate <= 15 Gbps and 10 Gbps < E-Tile Transceiver Data Rate <= 57.8 GbpsExample Requiring 9 Power Regulators
Power Pin Name Regulator Group Voltage Level (V) Supply Tolerance Power Source Regulator Sharing Notes
VCC 1

0.85

 ± 30mV Switcher (*) Share

Source VCC and VCCP from the same regulator, sharing the same voltage plane.

When implementing a filtered supply topology, you must consider the IR drop across the filter.
VCCP
VCCERAM 2 0.9 ± 30mV Switcher (*) Share

Connect the VCCERAM to a dedicated 0.9V power supply. You have the option to connect VCCPLLDIG_SDM to the same regulator as the VCCERAM power plane with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.
VCCPLLDIG_SDM Ferrite Bead Filter
VCCRT_GXE LC Filter

Connect VCCRT_GXE to a dedicated 0.9V power supply. You may source VCCRT_GXE from VCCERAM through an LC filter. You may also source VCCRTPLL_GXE from the same regulator as VCCRT_GXE through a ferrite bead.

When implementing a filtered supply topology, you must considered the IR drop across the filter.
VCCRTPLL_GXE Ferrite Bead Filter
VCCR_GXB[L,R] 3 1.03 ± 30mV Switcher (*) Share

You have the option to source the VCCR_GXB and VCCT_GXB from the same regulator when all the power rails require the same voltage level.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-tile or H-tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Intel® Stratix® 10 Device Datasheet.

VCCT_GXB[L,R]
VCCPT 4 1.8 ± 5% (**) Switcher (*) Share if 1.8V

You may source VCCPT and VCCBAT from the same regulator. You may connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel® Stratix® 10 devices.

When implementing a filtered supply topology, you must consider the IR drop across the filter.
VCCBAT Varies
VCCH_GXB[L,R] 1.8 Ferrite Bead Filter
VCCA_PLL 1.8
VCCPLL_SDM 1.8
VCCADC 1.8
VCCH_GXE 5 1.1 ± 5% (**) Switcher (*) Isolate Connect the VCCH_GXE to a dedicated 1.1V power supply.
VCCM_WORD_(BL,TL) 6 2.5 ± 100mV Switcher (*) Isolate

Connect VCCM_WORD_(BL,TL) to a 2.5V power supply.
VCCCLK_GXE Ferrite Bead Filter

Connect VCCCLK_GXE to a dedicated 2.5V power supply.

You have the option to share VCCCLK_GXE with VCCM_WORD if the VRM tolerance is ±100mV or better.

When sharing, filter the VCCCLK_GXE with a ferrite bead.
VCCIO_UIB_(BL,TL) 7 1.2 ± 30mV Switcher (*) Isolate Connect VCCIO_UIB_(BL,TL) to a 1.2V power supply.
VCCIO_SDM 8 1.8 ± 30mV Switcher (*) Share if 1.8V

You may source VCCIO, VCCIO_SDM, and VCCIO3V from the same regulator if they are at the same 1.8V voltage level.
VCCIO Varies
VCCIO3V
VCCFUSEWR_SDM 9 2.4 ± 50mV Switcher (*) Isolate Connect VCCFUSEWR_SDM to a dedicated 2.4V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8V power if the SDM fuses do not need to be written. Do not tie this pin to GND.

(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined as defined in note 7 of the Notes to Intel® Stratix® 10 Core Pins.

(**)The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Intel® Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) and the Intel® Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.

Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® Stratix® 10 TX device is provided in the following figure.

Figure 15. Example Power Supply Sharing Guidelines for Intel® Stratix® 10 MX (E-Tile) with L/H-Tile Transceiver Data Rate <= 15 Gbps and 10 Gbps < E-Tile Transceiver Data Rate <= 57.8 Gbps
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