SerialLite II IP Core User Guide

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ID 683179
Date 7/13/2021
Public
Document Table of Contents
Document Table of Contents x
1. SerialLite II IP Core Overview 2. SerialLite II IP Core Getting Started 3. SerialLite II IP Core Functional Description 4. SerialLite II IP Core Testbench 5. SerialLite II IP Core User Guide Archives 6. Document Revision History for the SerialLite II IP Core User Guide
1. SerialLite II IP Core Overview x
1.1. General Description 1.2. Performance and Resource Utilization
2. SerialLite II IP Core Getting Started x
2.1. Parameterize the IP Core 2.2. Set Up Simulation 2.3. Generate Files 2.4. Simulate the Design 2.5. Instantiate the IP Core 2.6. Compile and Program Specify Constraints 2.8. SerialLite II Parameter Settings
2.8. SerialLite II Parameter Settings x
2.8.1. Link Consistency 2.8.2. Data Rate 2.8.3. Reference Clock Frequency 2.8.4. Port Type 2.8.5. Self Synchronized Link Up 2.8.6. Scramble 2.8.7. Broadcast Mode 2.8.8. Lane Polarity and Order Reversal 2.8.9. Data Type 2.8.10. Packet Type 2.8.11. Flow Control Operation 2.8.12. Transmit/Receive FIFO Buffers 2.8.13. Data Integrity Protection: CRC 2.8.14. Transceiver Configuration 2.8.15. Error Handling 2.8.16. Optimizing the Implementation
2.8.10. Packet Type x
2.8.10.1. Retry-on-Error
2.8.11. Flow Control Operation x
2.8.11.1. Selecting the Proper Threshold Value 2.8.11.2. Selecting the Proper Pause Duration 2.8.11.3. Selecting the Proper Refresh Value 2.8.11.4. External Flow Control (When RX FIFO Size is 0)
2.8.14. Transceiver Configuration x
2.8.14.1. Voltage Output Differential (VOD) Control Settings 2.8.14.2. Pre-Emphasis Control Settings 2.8.14.3. Transmitter Buffer Power (VCCH) 2.8.14.4. Transceiver Reconfiguration Block 2.8.14.5. ALTGX Support Signals
2.8.16. Optimizing the Implementation x
2.8.16.1. Improving Performance 2.8.16.2. Minimizing Logic Utilization 2.8.16.3. Minimizing Memory Utilization
3. SerialLite II IP Core Functional Description x
3.1. Atlantic Interface 3.2. High-Speed Serial Interface 3.3. Clocks and Data Rates 3.4. Multiple Core Configuration 3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices 3.6. SerialLite II Signals 3.7. IP Core Verification
3.3. Clocks and Data Rates x
3.3.1. Aggregate Bandwidth 3.3.2. External Clock Modes 3.3.3. Internal Clocking Configurations 3.3.4. SerialLite II Deskew Support 3.3.5. SerialLite II Clocking Structure 3.3.6. SerialLite II Pin-Out Diagrams 3.3.7. Initialization and Restart
3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices x
3.5.1. Design Consideration 3.5.2. Parameter Settings For SerialLite II and Custom PHY IP Cores 3.5.3. Extra Signals Between SerialLite II and Custom PHY IP Cores
4. SerialLite II IP Core Testbench x
4.1. Testbench Files 4.2. Testbench Specifications 4.3. Simulation Flow 4.4. Testbench Components
4.3. Simulation Flow x
4.3.1. Running a Simulation 4.3.2. Simulation Pass and Fail Conditions
4.3.2. Simulation Pass and Fail Conditions x
4.3.2.1. Value Change Dump (VCD) File Generation (For the Verilog HDL Testbench) 4.3.2.2. Testbench Time-Out 4.3.2.3. Special Simulation Configuration Settings 4.3.2.4. Atlantic Receiver Behavior
4.4. Testbench Components x
AGEN AMON 4.4.3. Status Monitors 4.4.4. Clock and Reset Generator 4.4.5. Custom PHY IP Core 4.4.6. Example Testbench – Verilog HDL
1. SerialLite II IP Core Overview
2. SerialLite II IP Core Getting Started
3. SerialLite II IP Core Functional Description
4. SerialLite II IP Core Testbench
5. SerialLite II IP Core User Guide Archives
6. Document Revision History for the SerialLite II IP Core User Guide

1. SerialLite II IP Core Overview

Updated for:
Intel® Quartus® Prime Design Suite 16.1
IP Version 16.1
The SerialLite II IP core is a lightweight protocol suitable for packet and streaming data in chip-to-chip, board-to-board, and backplane applications.

The SerialLite II protocol offers low gate count and minimum data transfer latency. It provides reliable, high-speed transfers of packets between devices over serial links. The protocol defines packet encapsulation at the link layer and data encoding at the physical layer, and integrates transparently with existing networks without software support.

Table 1.  SerialLite II IP Core Release Information
Information Description
Version 16.1
Release Date October 2016
Ordering Code IP-SLITE2
Device Family Support
Intel® Arria® 10, Arria® V, Arria® II GX, Cyclone® V, Stratix® V, and Stratix® IV device families.
Note: Intel® Arria® 10 devices are indirectly supported by the SerialLite II IP core version 15.0 and later. If your design needs to implement SerialLite II interface in Intel® Arria® 10 devices, contact your local Intel representative or file a Service Request (SR) to obtain a design example, a guideline document, and a special license to enable the Intel® Quartus® Prime software to generate the FPGA configuration file (.sof) for the Intel® Arria® 10 devices.

Intel verifies that the current version of the Intel® Quartus® Prime software compiles the previous version of each IP core. The IP Core Release Notes and Errata report any exceptions to this verification. Intel does not verify compilation with IP core versions older than one release.

Table 2.  SerialLite II IP Core Features
Features Description
Physical layer features
  • 622 Mbps to 6.375 Gbps per lane1
  • Single or multiple lane support (up to 16 lanes)
  • 8-, 16-, or 32-bit data path per lane
  • Symmetric, asymmetric, unidirectional/simplex or broadcast mode
  • Optional payload scrambling
  • Full-duplex or self-synchronizing link state machine (LSM)
  • Channel bonding scalable up to 16 lanes
  • Synchronous or asynchronous operation
  • Automatic clock rate compensation for asynchronous use: ±100 and ±300 parts per million (ppm)
Link layer features
  • Atlantic™ interface compliant
  • Support for two user packet types: data packet and priority packet
  • Optional packet integrity protection using cyclic redundancy code (CRC-32 or CRC-16)
  • Optional link management packets
    • Retry-on-error for priority packets
    • Individual port (data/priority) flow control
  • Unrestricted data and priority packet size
  • Support for TimeQuest timing analyzer
  • Polarity reversal
  • Lane order reversal
  • IP functional simulation models for use in Intel-supported VHDL and Verilog HDL simulators
Related Information
1 For Intel® Arria® 10 devices, the IP core supports higher than 6.375 Gbps per lane.
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