O-RAN Intel® FPGA IP Design Example User Guide

ID 683218
Date 8/15/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

1. About the O-RAN Intel® FPGA IP Design Example

Updated for:
Intel® Quartus® Prime Design Suite 23.1
IP Version 1.9.1
The design example allows you to simulate, compile, and test your O-RAN IP instance on various development boards. The design example includes Ethernet IP, eCPRI IP, eCPRI IOPLL, PTP IOPLL, and a test wrapper.

The compiled hardware design example runs on the:

  • Intel Agilex® 7 F-Series Transceiver-SoC Development Kit for the E-tile design examples
  • Intel Agilex® 7 I-Series Transceiver-SoC Development Kit
  • Intel® Arria® 10 GX Signal Integrity Development Kit
  • Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit for the H-tile design examples
  • Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit for the E-tile design examples