Agilex™ 7 FPGA – Triple-Speed Ethernet and Onboard PHY Chip Reference Design Example

Agilex™ 7 FPGA – Triple-Speed Ethernet and Onboard PHY Chip Reference Design Example

821290
4/17/2024

Introduction

The Altera® FPGA Triple-Speed Ethernet and on-board PHY chip reference design demonstrates Ethernet operation between the Triple-Speed Ethernet IP core and onboard Marvell 88E1111 PHY chip through SGMII interface on Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit. TCL scripts are included to allow users test the auto-negotiation feature, internal MAC loopback, internal PHY loopback and TX/RX interop with external tester at data rate of 10/100/1000 Mbps. Packet statistics report will be generated as the output result of the internal loopback test.

Development Kit

Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit DK-SI-AGF014E3ES

Design Details

Device Family

Intel Agilex® 7 FPGAs and SoC FPGAs F-Series

Intel Agilex® 7 FPGA F-Series 014 (R24B) AGFB014R24B2E2V
Quartus Edition

Intel® Quartus® Prime Pro Edition
Quartus Version

24.1
IP Cores (5)
IP Core IP Core Category
Triple-Speed Ethernet Intel FPGA IP 1G Multi-rate Ethernet
IOPLL Intel FPGA IP PLL
Reset Release Intel FPGA IP Configuration and Programming
JTAG to Avalon Master Bridge Intel FPGA IP Memory Mapped
In-System Sources & Probes Intel FPGA IP Debug and Performance

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>

Development Kit

Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit DK-SI-AGF014E3ES

Design Details

Device Family

Intel Agilex® 7 FPGAs and SoC FPGAs F-Series

Intel Agilex® 7 FPGA F-Series 014 (R24B) AGFB014R24B2E2V
Quartus Edition

Intel® Quartus® Prime Pro Edition
Quartus Version

24.1