Article ID: 000091353 Content Type: Troubleshooting Last Reviewed: 08/18/2023

Why does the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* fails to simulate when using the Synopsys* VCS*/VCS MX* simulator?

Environment

  • Intel® Quartus® Prime Pro Edition
  • OS Independent family

    BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express*, you may observe an error message saying the simulation stopped due to inactivity when using the Synopsys* VCS*/VCS MX* simulator.

    Resolution

    To work around this problem, when starting the simulation, execute the following command: 
    sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final\ -debug_access+all" USER_DEFINED_SIM_OPTIONS="" TOP_LEVEL_NAME="pcie_ed_tb" | tee simulation.log

     

    This problem is fixed in version 22.3 of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series