Why does my timing degrade after implementing Distributed Sector Level based clock gating?

Distributed Sector Level based clock gating in Intel® Stratix® 10 or Intel Agilex® 7 devices results in a Hyper-Retiming restriction for any paths crossing from one clock sector into another, which can result in performance degradation. Distributed Sector Level-based clock gating is therefore not recommended for high-frequency clock domains or for large designs, which are implemented across multiple clock sectors and rely on Hyper-Retiming.

This Hyper-Retiming restriction is scheduled to be removed in a future release of the Intel® Quartus® Prime Pro Edition Software.