Article ID: 000086605 Content Type: Troubleshooting Last Reviewed: 02/15/2023

Critical Warning (21688): The total mutual inductance (Lm) of 1.0 V I/O < pin location > with surrounding 1.0 V I/O pins is < total mutual inductance value > nH. This is not allowed. The total mutual inductance must be less than or equal to < value

Environment

  • Intel® Quartus® Prime Standard Edition
  • Generic Component
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    You might receive this error when you place pins surrounding 1.0 V  I/O standard pins within the same bank despite meeting the total mutual inductance requirement based on mutual coupling spreadsheet for Intel® MAX® 10 FPGA. This is a known problem due to the outdated database for both the Intel® Quartus® Prime Software and the spreadsheet. 

    Resolution

    This problem is already fixed in the Intel® Quartus® Prime Software version 22.1.

     

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs