Description
The Stratix handbook version 3.1, Sep 2004 specifies /- 75 ps maximum skew for Enhanced PLLs using different E
clock outputs with the same counter settings. This value can be specified since the clock outputs will have the
same phase relationship. This specification also applies to output clocks with the same integer multiplier
(I.E. 100 MHz and 200 MHz clocks) because they have the same phase relationship.
Environment
BUILT IN - ARTICLE INTRO SECOND COMPONENT