Article ID: 000084329 Content Type: Troubleshooting Last Reviewed: 04/17/2023

Is there an known issue with the Early Power Estimator (EPE) tool for Stratix® V, Arria® V, and Cyclone® V devices when estimating off-chip power for Emulated LVDS I/O?

Environment

  • Quartus® II Software
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Yes, there is a known issue with the Early Power Estimator (EPE) tool versions 12.1 and earlier for Stratix® V, Arria® V, and Cyclone® V devices, where off-chip power (the power dissipated in the external resistor network) for Emulated LVDS I/O pins is not calculated.

    Resolution

    This bug has been fixed in EPE version 13.0

    Related Products

    This article applies to 16 products

    Acex® 1K
    Arria® V GX FPGA
    Arria® V GT FPGA
    Cyclone® V E FPGA
    Stratix® V E FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Stratix® V GX FPGA
    Cyclone® V GX FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA
    Arria® V GZ FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA