Error (10149): Verilog HDL Declaration error at core_debug.sv(1): identifier "seq_core_debug_pkg" is already declared in the present scope

This analysis and synthesis error message might be seen in the UniPHY example project when the UniPHY Intel® FPGA IP has these combination of settings :

• PHY Settings: Any of the PLL/DLL/OCT sharing mode options set to host or agent   
• Diagnostics: Enable EMIF On-Chip Debug Toolkit selected 

The problem is due to the core_debug.sv file being listed twice in the design example .qip file.

The workaround is to comment out one of the files in the design example .qip file. For example :

#set_global_assignment -library "<IP_name>_example" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "<IP_name>_example/submodules/<IP_name>_example_if0_s0_software/core_debug.sv"]

This problem is fixed starting with the Quartus® II software version 13.0.