Critical Issue
Designs that use the SDI MegaCore function targeting a Stratix V device fail to generate a simulation model in MegaWizard Plug-In Manager.
To generate a simulation model for your Stratix V design, follow these steps:
- In the Quartus II software, create a project and launch the MegaWizard Plug-In Manager
- Create a new custom megafunction variation, and select the desired SDI configuration
- On the EDA tab, make sure to turn off Generate simulation model
- Click OK
- In a command terminal, change the directory to the project folder to generate xcvr and sdi-library folders
- Run the quartus_map script as follows:
Verilog Example: quartus_map <proj_name>.v --simgen
--simgen_parameter="CBX_HDL_LANGUAGE=Verilog" --family="Stratix
V"
VHDL Example: quartus_map <proj_name>.vhd --simgen
--simgen_parameter="CBX_HDL_LANGUAGE=Vhdl" --family="Stratix V"
The <proj_name>.vo or vho file
gets generated at the project directory.