Beginning with the 10.0 release of the Quartus® II software, an optional software solution is available to work around the Cyclone® III M9K memory block read issue. For more details on the read bit issue, refer to the Cyclone III Device Family Errata Sheet. Depending on the device temperature grade selected, the software solution disables up to eight data bitlines in the widest data width modes.
To determine if your design has any M9K memory block usage that may be susceptible to the read issue, download the Tcl script below and save it in the design project directory. From the Quartus II GUI, point to Tcl Scripts on the Tools menu. Select the script and click Run to analyze your design. The script requires a successfully compiled design before it can perform the analysis.
The software solution can be applied using the fitter global setting for the design project. From the Quartus II menu, point to Settings on the Assignments menu, select the Fitter Settings page and click on the More Fitter Settings button. In the More Fitter Settings dialog box, choose the global setting
RAM Bit Reservation (Cyclone III) and select among the available options:
- Off - This option is the default and does not apply the software solution.
- Standard - This setting disables the necessary bitlines to ensure correct operation for all devices within the selected temperature range. For Commercial grade devices, this option disables up to four bitlines for M9K blocks that are configured in dual clock mode with data width of x32 or greater. For Industrial and Automotive grade devices, this option disables up to eight bitlines for M9K blocks that are configured in dual clock mode with data width of x32 or greater.
- Auto - This setting applies the solution to additional M9K data width modes (x16/x18) to provide extra margin. For Commercial grade devices, this option disables up to four bitlines for M9K blocks that are configured in dual clock mode with data width of x16 or greater. For Industrial and Automotive grade devices, this option disables up to eight bitlines for M9K blocks that are configured in dual clock mode with data width of x16 or greater or are configured in single clock mode with data width of x32 or greater.
- Maximum – This option disables up to eight bitlines for M9K blocks that are configured in dual clock mode with data width of x16 or greater, and in single clock mode with data width of x32 or greater. This setting is equivalent to the Auto setting when an Industrial device is selected.
The global setting can be overridden for each memory instance in the Assignment Editor by selecting the Assignment Name RAM Bit Reservation (Cyclone III). For the instance assignment, three options are available: Off, Auto, and Maximum. Selecting Auto or Maximum will disable similar number of bitlines as the global setting. The solution is applied to the specified memory instance regardless of the clock mode and the data width mode. To obtain the instance name, compile your design first, and check the RAM Summary section of the fitter report. Make sure to remove “|ALTSYNCRAM” from the end of the instance name when making the assignment.
Certain M9K mixed-width mode and byte-enable mode memories may not be supported for Commercial grade devices when the Standard or Auto global setting is applied. The fitter will issue an error for these cases. Those memory instances can be implemented by making an instance assignment with the Maximum setting.
Applying the software solution may require additional M9K resources. If a fitter error occurs, contact Altera for additional support.