Article ID: 000080904 Content Type: Troubleshooting Last Reviewed: 03/25/2013

Why does my Altera PLL fail to lock in simulation?

Environment

  • Quartus® II Subscription Edition
  • PLL
  • Simulation
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with the Altera PLL simulation model in the Quartus® II software versions 12.0 and earlier, the PLL may fail to lock in simulation if the areset port is not high at the beginning of simulation.

    This problem affects both gate-level and RTL simulation for designs targeting Stratix® V, Arria® V, and Cyclone® V devices.

    Resolution

    To avoid this problem, ensure that simulations using the Altera PLL begin with areset set high.

    This problem is fixed beginning with the Quartus II software version 12.0 SP1.

    Related Products

    This article applies to 14 products

    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Cyclone® V GX FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V E FPGA
    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA
    Arria® V GT FPGA
    Arria® V GX FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA
    Stratix® V E FPGA
    Stratix® V GX FPGA