Error: ATX PLL parameter 'output_clock_frequency' is set to an illegal value

You might see the following error if entering a high precision (number of decimal places) transceiver refclk and datarate into a transceiver PHY parameter editor on Stratix® V GX devices.

Error: ATX PLL parameter 'output_clock_frequency' is set to an illegal value

The error is due to an incorrect legality check in the Quartus® II software versions 12.1sp1 and earlier.

To work around this problem, you can reduce the precision of the refclk and datarate in the transceiver PHY parameter editor. The bandwidth of the transceiver Tx PLL and CDR will support your actual requirement.

This problem will be fixed in a future version of the Quartus II software.