Why do I see bit errors on RX channel 0 of transceiver block GXBL1 when I de-assert the gxb_powerdown signal of transceiver block GXBL0 when using Cyclone® IV GX EP4CGX150 and EP4CGX75 devices?

You might see bit errors on RX channel 0 of transceiver block GXBL1 when you de-assert the gxb_powerdown signal of transceiver block GXBL0 when using Cyclone® IV GX EP4CGX150 and EP4CGX75 devices due to coupling inside the device.

Designs that might be affected are:

• Cyclone IV GX EP4CGX150 and EP4CGX75 devices that use transceiver banks GXBL0 and GXBL1 
• RX channel 0 in transceiver bank GXBL1 is used 
• TX Channel 3 in transceiver bank GXBL0 is used 
• The gxb_powerdown signals of transceiver banks GXBL0 and GXBL1 are controlled independently.

Affected designs may need to be resynchronized.

To work around this problem, do not use the gxb_powerdown signal for transceiver bank GXBL0. Instead you can assert the pll_areset, tx_digitalreset, rx_analogreset, and rx_digitalreset signals.