Article ID: 000079664 Content Type: Error Messages Last Reviewed: 04/13/2023

Error: IR FIFO USERDES Block node 'lvds_rx:lvds_rx_inst0|altlvds_rx:ALTLVDS_RX_component|lvds_rx_lvds_rx:auto_generated|sd2' is not properly connected on the 'WRITECLK' port

Environment

  • Quartus® II Subscription Edition
  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 12.1 and later, you might see this error in Cyclone® V devices when using the ALTLVDS_RX Intel FPGA IP in external phase-locked loop (PLL) mode.

    Error: IR FIFO USERDES Block node 'lvds_rx:lvds_rx_inst0|altlvds_rx:ALTLVDS_RX_component|lvds_rx_lvds_rx:auto_generated|sd2' is not properly connected on the 'WRITECLK' port. It must be connected to one of the valid ports listed below.Info: Can be connected to LOADEN port of arriav_pll_lvds_output WYSIWYGInfo: Can be connected to OUTCLK port of generic_pll WYSIWYGInfo: Can be connected to LVDSCLK port of cyclonev_pll_lvds_output WYSIWYGInfo: Can be connected to OUTCLK port of arriav_clkena WYSIWYG

    Resolution

    To work around this problem, an LVDS buffer must be inserted between the external PLL and the ALTLVDS instance on the rx_inclock and the rx_enable ports.

    Refer to the related solution under the Related Articles section to learn how to add an intermediate LVDS buffer between the external PLL and ALTLVDS Intel FPGA IP.

    Related Products

    This article applies to 6 products

    Cyclone® V GT FPGA
    Cyclone® V E FPGA
    Cyclone® V GX FPGA
    Cyclone® V SX SoC FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA