Article ID: 000079638 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Have the Stratix III device timing models for DDR3 write leveling delay chains been updated since the release of the Quartus II software version 9.0?

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Description
Yes, since the release of the Quartus® II software version 9.0 the timing models for the write leveling delay chains have been updated for Stratix® III devices. These delay chains were incorrectly modeled in the Quartus II software versions 9.0 and earlier. The device timing models and the DDR3 SDRAM High-Performance Controller MegaCore IP in the Quartus II software version 9.0 SP1 have been updated to resolve this issue. This update eliminates the possibility of hardware functional failures in your designs implementing DDR3 DIMM interfaces or DDR3 component interfaces with leveling (daisy-chain topology for address/command signals).
 
This issue impacts all Stratix III designs implementing leveled DDR3 interfaces using the DDR3 SDRAM High-Performance Controller MegaCore or ALTMEMPHY megafunction. If your design implements DDR3 interfaces with leveling, follow these steps to fix the problem:
 

Figure 1