Yes, you may encounter an issue with the output clock frequency when setting duty cycle values other than 50% in the PLL Intel FPGA IP. This can occur when using the Quartus® II software version 13.0sp1 and earlier.
The problem occurs if the C-Counter Hi Divide and C-Counter Low Divide parameters are calculated incorrectly by the PLL Intel FPGA IP. The Compilation report => Fitter => Resource Section => PLL Usage Summary will show the actual output clock frequency. If the reported output clock frequency is not correct, then the C-Counter Hi Divide or C-Counter Low Divide parameter is not correct.
The C counters are used to divide the voltage-controlled oscillator (VCO) frequency to the desired output frequency. The sum of the C-Counter Hi Divide and C-Counter Low Divide parameters is the resulting divider value of the VCO frequency.
For example, if the VCO is running at 840 MHz, and the desired output clock is 105 MHz, then a total divide value of 8 is required. For a 50% duty cycle, the high and low counts should be divided evenly between the C-Counter Hi Divide and C-Counter Low Divide parameters, in which the divide value for each parameter is 4. To create other duty cycle values, you can adjust the C-Counter Hi Divide and C-Counter Low Divide parameters as required. You need to ensure the sum of these parameters is equal to the total divide value in order to generate the desired output clock frequency.
If the total divide value is an odd value, then you need to turn on the C-Counter Odd Divide Enable parameter if a 50% duty cycle is required. For example, if the VCO is running at 840 MHz and the desired output clock frequency is 120 MHz, then a total divide value of 7 is required. In this case the C-Counter Hi Divide parameter would be 4, the C-Counter Low Divide parameter would be 3, and set the C-Counter Odd Divide Enable parameter to True. If a duty cycle other than 50% is required, you will need to adjust the C-Counter Hi Divide parameter and C-Counter Low Divide parameter as required. You need to ensure the sum of these parameters is equal to the total divide value in order to generate the desired output clock frequency.
To fix this problem in your design, open the <PLL instance name>_0002.v file and locate the C-Counter Hi Divide and C-Counter Low Divide parameters for the affected output clock(s). Adjust these parameters as required to create the correct output clock frequency and desired duty cycle.
Referring to the examples above, if the VCO is running at 840 MHz and the desired output clock frequency is 105 MHz with a 12.5% duty cycle, the following parameters will be required:
- C-Counter Hi Divide = 1
- C-Counter Low Divide = 7
- C-Counter Odd Divide Enable = False
Due to the problem in the PLL Intel FPGA IP calculation, set the following parameters for a 120 MHz output clock frequency:
- C-Counter Hi Divide = 1
- C-Counter Low Divide = 6
- C-Counter Odd Divide Enable = True
To fix the parameters in this example, the C-Counter Low Divide parameter should be set to 7, and the C-Counter Odd Divide Enable parameter should be set to False in the <PLL instance name>_0002.v file.