Article ID: 000077446 Content Type: Error Messages Last Reviewed: 04/18/2023

Critical Warning(18234): ATX PLLs <hierarchy>:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst and <hierarchy>:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst are <number> ATX PLLs apart.

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 18.1, an incorrect critical warning may occur when you compile the design, including two ATX PLLs operating at the same VCO frequency (within 100 MHz) even if the placement rules below have been followed (Critical warning below after the bullet list).

    • For ATX PLL VCO frequencies between 7.2 GHz and 11.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz), they must be placed 7 ATX PLLs apart (skip 6).
    • For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz) and drive GX channels, they must be placed 4 ATX PLLs apart (skip 3).
    • For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz) and drive GT channels, they must be placed 3 ATX PLLs apart (skip 2).
    • For two ATX PLLs providing the serial clock for PCIe*/PIPE Gen3, they must be placed 4 ATX PLL apart (skip 3).

    Critical Warning(18234): ATX PLLs :xcvr_atx_pll_a10_0|a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst and :xcvr_atx_pll_a10_0|a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst are ATX PLLs apart. For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz), they must be placed 5 ATX PLLs apart.

    Resolution

    This problem has been fixed in Intel® Quartus® Prime Pro Edition Software 19.1 version. 

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs