Article ID: 000077362 Content Type: Troubleshooting Last Reviewed: 05/15/2017

Why does the "rx_10g_frame_mfrm_err" flag assert during an Interlaken non-framing layer control word when using a Stratix V device Native PHY IP with the Interlaken Preset?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime software, both the "rx_10g_mfrm_err" flag and "rx_10g_control[8]" status bit might assert during Interlaken non-framing layer control words when using the Stratix V device Native PHY IP with the Interlaken Preset.

    Resolution

    To workaround this issue, ignore the "rx_10g_mfrm_err" flag and "rx_10g_control[8]" status bit during non-framing layer control word locations within the Interlaken metaframe. 

    Related Products

    This article applies to 3 products

    Stratix® V GX FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA