Article ID: 000077313 Content Type: Troubleshooting Last Reviewed: 08/15/2019

Why doesn’t the tx_pma_elecidle signal on the Intel® Arria® 10 or Cyclone® 10 GX device Native PHY IP put the transceiver TX pins in a tristate or high-impedance mode?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Transceiver Native PHY Intel® Arria® 10 Cyclone® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Asserting the tx_pma_elecidle signal on the Intel Arria 10 or Cyclone 10 GX device Native PHY IP does not tristate or put the transceiver TX pins in a high-impedance mode.

    Asserting the tx_pma_elecidle signal on the Intel Arria 10 or Cyclone 10 GX device Native PHY IP stops data transmission and causes the output signal to exhibit the Transmitter Vocm on both P and N pins of the differential pair.

    The TX termination remains connected to the Vcm generator when the tx_pma_elecidle signal is asserted.   

    Resolution

    This information may be added to a future version of the Intel Arria 10 Transceiver PHY User Guide and Intel Cyclone 10 GX Transceiver User Guide.

    Related Products

    This article applies to 2 products

    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Cyclone® 10 GX FPGA