The Quartus® II software version 7.2 Service Pack 2 incorrectly configures four device pins in Stratix® III 3SL340 devices in certain package options (see table below). This is due to incorrect input register and delay chain settings used in the Quartus II Software. The affected input pin names are PLL_R1_CLKn, PLL_R1_CLKp, PLL_R4_CLKn, and PLL_R4_CLKp. Altera recommends applying the software patch 72SP2 2.03 to fix the issue.
To obtain the patch, contact Altera Technical Support by submitting a Service Request at mysupport.altera.com.
Stratix III 3SL340 Device Package |
Affected Pins |
F1517 |
AU1, AU2, C1, and C2 |
F1760 |
AY1, AY2, C1, and C2 |
H1152 |
None |