Description
For Stratix® family designs (Stratix and Stratix GX) in the Quartus®II software version 6.1 and 7.0, the Node Finder does not list fast PLL output clock nets when you use the SignalTap® II: post fitting filter. To use a fast PLL clock output as the acquisition clock for the SignalTap II logic analyzer, type in the name of the post-fit clock net name you want to use. You can find this net name with the Technology Map Viewer.
This problem is fixed beginning with the Quartus II software version 7.1.