Article ID: 000077016 Content Type: Troubleshooting Last Reviewed: 05/27/2014

What is the Instruction Register (IR) length of the Hard Processor System (HPS) JTAG pins on Cyclone V and Arria V SoC devices?

Environment

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Description

The HPS JTAG pins are not intended for boundary scan for Cyclone® V and Arria® V SoC devices.  The HPS JTAG pins do not have a Boundary-Scan Description Language (.bsd) file, but if you have this port included in your JTAG chain, you will need to know the IR length.

The IR length is 4 bits and the BYPASS instruction is 0xF (the bypass instruction is always all ones according to IEEE1149.1).

Related Products

This article applies to 5 products

Cyclone® V SE SoC FPGA
Arria® V ST SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX SoC FPGA
Arria® V SX SoC FPGA