Article ID: 000076875 Content Type: Troubleshooting Last Reviewed: 04/03/2019

Why does the Pixel Clock Recovery (PCR) module in the DisplayPort Intel® FPGA IP Core design example fail at high temperature?

Environment

  • Intel® Quartus® Prime Pro Edition
  • DisplayPort Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

     

    You may see the Altera® PLL IP in the Bitec pixel clock recovery IP lose lock after dynamic reconfiguration when the FPGA device is raised above room temperature. In this event, the reset_out signal of the Bitec pixel clock recovery IP is asserted and no video is observed at the monitor. When the FPGA device is cooled, the video at the monitor resumes, Altera PLL IP regains lock and the Bitec pixel clock recovery IP reset_out signal is not asserted.  The root cause of the problem is the incorrect PLL VCO post divider setting configured by the Bitec pixel clock recovery IP. The incorrect setting causes the VCO frequency to exceed the legal range as specified in device datasheet.

    Resolution

    A patch is available to fix this problem for the Intel® Quartus® Prime Standard Edition software version 17.1 and for the Intel® Quartus® Prime Standard Edition software version 17.1 Update 1 from the appropriate link below:

    For v17.1:

    Download patch 0.16std for Windows (.exe)

    Download patch 0.16std for Linux (.run)

    Download the Readme patch 0.16std (.txt)

    For v17.1.1

    Download patch 1.19std for Windows (.exe)

    Download patch 1.19std for Linux (.run)

    Download the Readme patch 1.19std (.txt)

     

    This problem has been fixed starting in Intel® Quartus® Prime Standard Edition software version 19.1.  

    Related Products

    This article applies to 3 products

    Cyclone® V FPGAs and SoC FPGAs
    Arria® V FPGAs and SoC FPGAs
    Stratix® V FPGAs