Article ID: 000076751 Content Type: Troubleshooting Last Reviewed: 02/13/2023

In Intel® Stratix® 10 TX and MX device how should the VCCIO_HPS and VCCPLL_HPS power pins be connected when not using HPS?

Environment

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Description

If you do not intend to use the HPS in an Intel® Stratix® 10 TX and MX device, you must still provide power to the VCCIO_HPS and  VCCPLL_HPS pins. Do not leave the VCCIO_HPS and  VCCPLL_HPS power pins floating or connect them to GND.

 

Resolution

N/A

Related Products

This article applies to 2 products

Intel® Stratix® 10 MX FPGA
Intel® Stratix® 10 TX FPGA

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