Article ID: 000076535 Content Type: Troubleshooting Last Reviewed: 02/14/2023

Why does the Intel® P-Tile Avalon® Memory Mapped IP for PCI Express* 4.0x4 Root Port design example reports an error during compilation?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.1 or earlier, the Intel® P-Tile Avalon® Memory Mapped IP for PCI Express* 4.0x4 Root Port design example reports an error during compilation.

    Error(21410): Verilog HDL error at s10_rp_avmm_master_hwtcl.v(130): event control statement inside subprogram is not supported for synthesis

    Resolution

    To work around this, it is necessary to generate the simulation and synthesis file separately and re-compile the design example.

    This problem is fixed starting with the Intel® Quartus® Prime Pro/Standard Edition Software version 22.4.

     

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 DX FPGA
    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series