Article ID: 000075685 Content Type: Troubleshooting Last Reviewed: 12/23/2022

Why is the rx_st_valid signal not asserted in the Intel® L- and H-tile Avalon® Streaming for PCI Express* IP when receiving an Unsupported Request (UR) completion?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with the Intel® Quartus® Prime Pro Edition Software version 20.4 and earlier, you may encounter the above problem when receiving an Unsupported Request (UR) completion on physical functions(PF) 2 and 3.

    Resolution

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.1.

    Related Products

    This article applies to 6 products

    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Intel® Stratix® 10 NX FPGA
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA
    Intel® Stratix® 10 SX SoC FPGA