Article ID: 000075596 Content Type: Troubleshooting Last Reviewed: 01/03/2023

Why do I see clock crossing timing failures for the rx_lanes_aligned signal in the Interlaken (2nd Generation) Intel® FPGA IP design example?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interlaken (2nd Generation) Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.1 and earlier, the rx_lanes_aligned signal was not synced to usr_clk before exiting to the intellectual property (IP) core. This can cause metastability at the user logic if it is not synchronized by the user. The metastable issue can propagate to the user logic even if the change of aligned is not frequent.

    Resolution

    To work around this, Intel recommends adding a synchronizer to the rx_lanes_aligned signal onto the usr_clk domain.

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.3.

    Related Products

    This article applies to 5 products

    Intel® Stratix® 10 NX FPGA
    Intel® Stratix® 10 MX FPGA
    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
    Intel® Stratix® 10 DX FPGA
    Intel® Stratix® 10 TX FPGA