Article ID: 000075587 Content Type: Troubleshooting Last Reviewed: 08/16/2023

Why does the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express design example use the CML I/O standard on the PCI Express reference clock input pins?

Environment

  • Intel® Quartus® Prime Pro Edition
  • example-design-components
  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express design example, the default I/O standard for the PCI Express reference clock input pins is CML.

     

    Resolution

    According to the PCI Express Base Specification and the Intel Agilex® Device Family Pin Connection Guidelines, the reference clock input pins should be set to HCSL I/O standard.

    This problem is fixed in Intel® Quartus® Prime Pro Edition Software 21.3. 

     

     

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series