Article ID: 000075491 Content Type: Troubleshooting Last Reviewed: 07/02/2021

Why does my design including an R-Tile Avalon Streaming Intel® FPGA IP for PCI Express* fails to successfully go through  reconfiguration or CVP Update operation?

Environment

  • Intel® Quartus® Prime Pro Edition
  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 21.2, you may experience an error while reconfiguring or performing a CVP update on your device if there is no stable free running clock signal on the reference clock pins (REFCLK_GXR[R,L [14A,14C,15A,15C]_CH[0,1]P) of the R-Tile before going through the reconfiguration process.

    The problem will not affect your device during the first configuration process even if there is no stable free running clock signal on the reference clock pins (REFCLK_GXR[R,L [14A,14C,15A,15C]_CH[0,1]P).

    Resolution

    To work around this problem, provide an stable free running clock signal on the reference clock pins (REFCLK_GXR[R,L [14A,14C,15A,15C]_CH[0,1]P) of the R-Tile before starting a device reconfiguration operation.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series