Article ID: 000075144 Content Type: Troubleshooting Last Reviewed: 06/30/2014

Arria V and Cyclone V HPS Designs May Fail to Compile with NC-Sim

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    This problem affects Arria V And Cyclone V HPS interfaces.

    The NC-Sim simulator requires that each file contain a time scale directive. Some of the Altera Verilog or System Verilog files for HPS simulation might be missing the required time scale.

    Resolution

    The workaround for this issue is to add the following to any files that are missing the time scale directive:

    timescale 1 ps / 1 ps

    This issue will be fixed in a future version.

    Related Products

    This article applies to 1 products

    Arria® V FPGAs and SoC FPGAs