The phase-locked loop (PLL) in Stratix® V, Arria® V, or Cyclone® V devices might fail to reconfigure with the waitrequest signal of the PLL reconfiguration intellectual property (IP) being stucked at ‘1’. This is observed to take place for certain compilation seeds and might happen if the Physical Synthesis option in the Fitter (Advanced) settings of the Intel® Quartus® Prime Software is enabled.
To work around this problem, disable the following settings in the Intel® Quartus® Prime Software:
Go to Assignments -> Settings -> Compiler Settings -> Fitter (Advanced) Settings:
Set Enable Physical Synthesis for Combinational Logic for Area to OFF.
Set Enable Physical Synthesis for Combinational Logic for Performance to OFF.
This problem is known to affect only the dynamic reconfiguration instance and hence the physical synthesis setting can be disabled only for the PLL Reconfig IP variation, if needed.