Redefining Compute Through Process and Packaging

Driving the next era of computing though transistor and packaging innovations.

A New Paradigm for Moore’s Law

Intel set the pace for computing innovation in the PC era with Moore’s Law. As data grows exponentially, so does the need for powerful chips to move, store, and process data across a distributed landscape.

Moore’s Law is as important as ever, but there’s more to it than meets the eye. Intel is powering the data-centric era with synchronized and coarchitected advances in transistors, packaging, and chip design. No other company has our fab foundation, in-house research and development capabilities, innovation pipeline, and integrated device manufacturer advantage—a unique set of complementary capabilities that will redefine what’s possible in computing.

From Sand to Silicon: The Making of a Microchip


Check out this video to learn more about how we turn sand into the silicon chips that power the world.

Transistors: Performance Leaps, Measured in Nanometers

A microprocessor may be the most complex manufactured product made by humans. Producing it takes hundreds of steps in the world’s cleanest environment, carried out by skilled experts who are meticulously trained to move atoms and molecules.

Each microprocessor is made up of billions of tiny electrical switches called transistors. As transistors grow smaller, computing devices become smarter, faster, and more efficient. But shrinking transistors is no longer enough to deliver leaps in performance. Radical design improvements are also needed.

Process Innovations Drives Progress

Intel’s process innovations help drive our progress. Our goal is to continue to transistor density through node transitions. Between these shrinks, we are planning enhancements through intranode innovations—ultimately supporting a regular cadence of performance improvements for our products.

Smaller and Faster with 3D Transistors

With our leadership in manufacturing the fin-shaped field-effect transistor (FinFET), Intel raised the 2D transistor channel into the third dimension, greatly improving control of electrons flowing through the channel. These transistors operate at a lower voltage with lower leakage, providing an unprecedented combination of improved performance and energy efficiency. As a result, transistors are smaller, faster, and use less power than ever before.

Refining the FinFET

We have been continuously refining the FinFET since its introduction nearly a decade ago. At the 14nm node, we drove regular increases in transistor-level frequency over several generations, ultimately delivering the equivalent of a full-node of performance improvement through intranode enhancements.

We introduced our third iteration of FinFET transistors at the 10nm node, continuing our journey of refining this technology. With our first-generation 10nm FinFET, we focused on delivering 2.7x “hyperscaling” density over the previous node. This was driven by key innovations such as Contact Over Active Gate (COAG), which moved beyond the transistor device to the metal interconnects and ultimately the cell level.

Redefining the FinFET

Coming into 2020, our design teams were asking for even more performance headroom to deliver the product pipeline our customers required. After years of refining the FinFET platform, we are redefining it to deliver an unprecedented level of performance uplift with our new SuperFin technology.

SuperFin leverages a combination of innovations across the entire process stack, from the transistor channel to the top metal layers. A key breakthrough is a new Super MIM capacitor, which delivers a 5x increase in capacitance within the same footprint as industry standard approaches. This industry-first technology drives a voltage reduction that translates to dramatically improved product performance.

The combined power of these innovations enable us to deliver a dramatic process performance boost that will take Intel products to a new level in 2020 and beyond. In one single intranode enhancement, we delivered nearly the equivalent performance of a full-node transition.

Upcoming Innovations

Intel’s in-house research and development is unmatched in the industry. See how our researchers are continuing to make breakthroughs in transistor design.

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Packaging: A Catalyst for Product Innovation

As the physical interface between processor and motherboard, a chip’s packaging plays a critical role in product-level performance. Advanced packaging techniques will allow diverse computing engines to be integrated across multiple process technologies, enabling completely new approaches in system architecture.

Embedded Multi-Die Interconnect Bridge (EMIB)

EMIB is a cost-effective approach to connecting multiple, heterogeneous die into a single package. While other 2.5D strategies use a large silicon interposer, EMIB uses a very small bridge die with multiple routing layers. Having many embedded bridges in a single substrate provides extremely high I/O and well-controlled interconnect between multiple die.

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Industry-First 3D Stacking with Foveros

Our Foveros packaging technology uses 3D stacking to enable logic-on-logic integration. This provides tremendous flexibility for designers to mix and match technology IP blocks with various memory and I/O elements in new device form factors. Products can be broken into smaller chiplets where I/O, SRAM, and power delivery circuits are fabricated in a base die and high-performance logic chiplets are stacked on top.

Discover how

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Next-Generation Packaging

Intel’s latest packaging capabilities are unlocking new customer designs. Our Co-EMIB technology allows for the interconnection of Foveros elements with essentially the performance of a single chip. With Omni-Directional Interconnect (ODI), designers get even greater flexibility for communication among chiplets in a package.

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Integrated Advantage

As an integrated device manufacturer (IDM), Intel combines our powerful compute engines with leadership packaging to deliver unmatched product integration. Our complementary capabilities mean we can fully integrate our design, process, and packaging into products that are truly the best in their class. And with our portfolio of CPUs, FPGAs, accelerators, and graphics processing chips, our architects have the best flexibility to pick the right transistor for the product.

Industry-First Hybrid Architecture

Intel’s unique processor, code-named “Lakefield,” combines a hybrid CPU with our Foveros 3D packaging technology. This architecture offers more flexibility to innovate on design, form factor, and experience.

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Six Pillars of Technology Innovation for the Next Era of Computing

Intel is innovating across six pillars of technology development to unleash the power of data for the industry and our customers.

Disclaimer

Intel® technologies' features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Performance varies depending on system configuration. No product or component can be absolutely secure. Check with your system manufacturer or retailer or learn more at intel.com.au.

All information provided here is subject to change without notice.