Product Collection
Stratix® V GS FPGA
Marketing Status
Launched
Launch Date
2010
Lithography
28 nm

Resources

Logic Elements (LE)
695000
Adaptive Logic Modules (ALM)
262400
Adaptive Logic Module (ALM) Registers
1049600
Fabric and I/O Phase-Locked Loops (PLLs)
28
Maximum Embedded Memory
58.01 Mb
Digital Signal Processing (DSP) Blocks
1963
Digital Signal Processing (DSP) Format
Multiply and Accumulate, Variable Precision, Fixed Point (hard IP)
Hard Memory Controllers
No
External Memory Interfaces (EMIF)
DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3

I/O Specifications

Maximum User I/O Count
840
I/O Standards Support
3.0 V LVTTL, 1.2 V to 3.0 V LVCMOS, SSTL, HSTL, HSUL, Differential SSTL, Differential HSTL, Differential HSUL, LVDS, Mini-LVDS, RSDS, LVPECL, BLVDS
Maximum LVDS Pairs
420
Maximum Non-Return to Zero (NRZ) Transceivers
48
Maximum Non-Return to Zero (NRZ) Data Rate
14.1 Gbps
Transceiver Protocol Hard IP
PCIe Gen3

Package Specifications

Package Options
F1517, F1932

Supplemental Information