Product Collection
MAX® V CPLD
Status
Launched
Launch Date
2010
Lithography
180 nm

Resources

Logic Elements (LE)
40
Equivalent Macrocells
32
Pin-to-pin Delay
7.5 ns
User Flash Memory
8 Kb
Logic Convertible To Memory
Yes

Features

Internal Oscillator
Yes
Fast Power-on Reset
Yes
Boundary-scan JTAG
Yes
JTAG ISP
Yes
Fast Input Registers
Yes
Programmable Register Power-up
Yes
JTAG Translator
Yes
Real-time ISP
Yes
MultiVolt I/Os†
1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V
I/O Power Banks
2
Maximum Output Enables
54
LVTTL/LVCMOS
Yes
Emulated LVDS Outputs
Yes
Schmitt Triggers
Yes
Programmable Slew Rate
Yes
Programmable Pull-up Resistors
Yes
Programmable GND Pins
Yes
Open-drain Outputs
Yes
Bus Hold
Yes

Package Specifications

Package Options
M64, E64
Package Size
4.5mm x 4.5mm, 9mm x 9mm

Supplemental Information

Additional Information