Intel's Arria® V SoC FPGA is the industry's highest performance 28 nm SoC FPGA with the lowest total power for midrange applications such as remote radio units, 10G/40G line cards, medical imaging, and broadcast studio equipment. The combination of a hard processor system (HPS) consisting of a dual-core ARM* Cortex*-A9 processor, peripherals, and memory interfaces with flexible 28 nm FPGA fabric lets you reduce system power, cost, and board space.
Family Variants
Arria® V SX SoC FPGA
Intel® SoC FPGA with ARM-based HPS and 6.5536 Gbps backplane-capable transceivers
Arria® V ST SoC FPGA
Intel SoC FPGA with ARM-based HPS and 10.3125 Gbps transceivers
Benefits
Architecture Matters
SoC FPGAs are more than the sum or their parts. It is critically important to understand how the processor and FPGA systems work together to accomplish each task. When you choose an SoC FPGA for your next design, architecture matters. Intel® SoC FPGAs are designed to:
- Preserve the flexibility of processor boot / FPGA configuration sequence, system response to processor reset, and independent memory interfaces of a two-chip solution
- Maintain data integrity and reliability with integrated ECC
- Protect DRAM memory shared by the processor and FPGA with an integrated memory protection unit
- Enable system-level debug with Intel's FPGA-adaptive debugging for unmatched visibility and control of the whole device
Not All SoC FPGAs Are Created Equal. Architecture Matters.
Learn how to choose the right SoC FPGA for your application from our extensive set of resources, including a short series of videos from processor expert Jim Turley.
Easy Migration Path to Arria® 10 SoC FPGA
Features
Arria® V SoC FPGA Hard Processor System Overview
| Device | All Arria® V SoC FPGA Devices (SX, ST) |
|---|---|
| Processor | Dual-core ARM Cortex-A9 MPCore processor with ARM CoreSight* debug and trace technology
|
| Coprocessors | ARM NEON* media processing engine with Vector Floating-Point (VFP) v3 double-precision floating point unit for each processor, Snoop Control Unit (SCU), Acceleration Coherency Port (ACP) |
| Level 1 cache | 32 KB L1 instruction cache, 32 KB L1 data cache |
| Level 2 cache | 512 KB shared L2 cache |
| On-chip memory | 64 KB on-chip RAM, 64 KB on-chip ROM |
| HPS hard memory controller | Multiport SDRAM controller with support for DDR2, DDR3, DDR3L, and LPDDR2 with optional error correction code (ECC) support |
| Quad serial peripheral interface (SPI) flash controller | Supports SPIx1, SPIx2, or SPIx4 (quad SPI) serial NOR flash devices Up to four chip selects |
| SD/SDIO/MMC controller | Supports SD, eSD, SDIO, eSDIO, MMC, eMMC, and CE-ATA with integrated DMA |
| NAND flash controller | Supports 8 bit ONFI 1.0 NAND flash devices Programmable hardware ECC for Single-Level Cell (SLC) and Multi-Level Cell (MLC) devices |
| Ethernet media access controller (EMAC) | 2 x 10/100/1000 EMAC with RGMII external PHY interface and integrated DMA |
| USB On-The-Go controller (OTG) | 2 x USB 2.0 OTG controllers with ULPI external PHY interface and integrated DMA |
| UART controller | 2 x UART 16550 compatible |
| SPI controller | 2 x SPI masters 2 x SPI slaves |
| I2C controller | 4 x I2C |
| General-purpose I/O (GPIO) | Up to 71 GPIO and 14 input-only pins, with digital de-bounce and configurable interrupt mode |
| Direct memory access (DMA) controller | 8-channel direct memory access (DMA) Supports flow control with 31 peripheral handshake interfaces |
| Timers | Private interval and watchdog timer for each processor Global timer for processor subsystem 4X general-purpose timers 2X watchdog timers |
| Maximum HPS I/O | 208 |
| HPS phased-locked loops (PLLs) | 3 |
Industry’s Highest Performance 28 nm SoC FPGA
- Up to 1.05 GHz dual-core ARM Cortex-A9 MPCore processor
- Four hardened 32-bit memory controllers with up to 533 MHz memory bus speed and optional error correction code (ECC)
- Processor to FPGA interconnect with >125 Gbps peak total bandwidth
Lowest System Power for Midrange Applications
- Integration of multiple components into a single chip
- Lowest power transceivers with speeds up to 10.3125 Gbps
- Based on low power TSMC 28LP process
Multiple Benefits to System Cost
- Integration of multiple components into a single chip
- PCB cost and trace savings from integration of processor, FPGA and DSP into a single device
- No power-off sequencing requirements
Intel® Enpirion® Power Solutions
Intel® Enpirion® Power Solutions are high-frequency DC-DC step-down power converters designed and validated for Intel® FPGA, CPLD, and SoCs. These robust, easy-to-use power modules integrate nearly all of the components needed to build a power supply – saving you board space and simplifying the design process.
Design Tools
Intel® SoC FPGA Embedded Development Suite
Jump start your firmware and application software development with our Intel® SoC FPGA Embedded Development Suite (SoC EDS), a comprehensive tool suite with:
- Development tools
- Utility programs
- Run-time software
- Application examples
At the heart of the SoC EDS is the exclusive ARM* Development Studio 5* (DS-5*) Intel SoC FPGA Edition. This toolkit combines the ARM DS-5* advanced multicore debugging capabilities with FPGA-adaptivity for unprecedented full-chip debugging visibility and control.
Intel® Quartus® Prime Software Suite
Intel® Quartus® Prime Software Suite provides everything you need to design with Intel SoC FPGAs. It is a complete development package that comes with a user-friendly GUI and technology to help you turn your ideas into reality. The Intel Quartus Prime software includes productivity tools to make it easy to build your design, such as:
- Intel FPGA SDK for OpenCL™ Technology
- Platform Designer (formerly Qsys)
- System Console debugging toolkit
- Transceiver Toolkit
- Timing Analyzer
- Power Analyzer
Ecosystem
Intel® SoC FPGAs are ARM* processor-based and inherit the strength of the ARM ecosystem. Intel, our ecosystem partners, and the Intel SoC FPGA user community provide a wide range of options to meet your SoC FPGA development needs. There are a number of options for operating systems, development tools, intellectual property (IP) cores, and professional services. Many are provided by ecosystem partners.
Operating Systems
Arria® V SoC FPGA includes a sophisticated high-performance multicore ARM* Cortex*-A9 processor. This processor can be used for a wide range of functions from very simple bare-metal applications running on one of the available cores to high-bandwidth, low-latency , real-time operations.
Development Tools
For professional quality development tools including JTAG debuggers and instruction trace functions.
IP Cores
Intel SoC FPGAs are supported by a wide range of Intel FPGA and third-party soft Intellectual Property (IP) cores. These blocks can be instantiated in the FPGA portion of the SoC FPGA device.
Nios® II Soft Processor
The Nios® II processor, the world's most versatile processor, according to Gartner Research, is the most widely used soft processor in the FPGA industry.
Design Services Network
Design Service Network (DSN) members offer an extensive portfolio of design services, IP, and products that can help customers meet challenging product development needs, lower risk, and accelerate time to market.
Boards
Intel SoC FPGA-based boards are available from Intel and ecosystem partners. Boards can be standalone or system on module (SoM) configuration.
Applications
The Arria® V SoC FPGAs have been designed to meet the performance, power, and cost requirements for applications such as:
- Wireless infrastructure equipment including remote radio units and mobile backhaul
- Wireline 10G/40G line cards, bridges and aggregation, GPON
- Broadcast studio and distribution equipment including professional A/V and video conferencing
- Military guidance, control, and intelligence equipment
- Test and measurement equipment
- Medical imaging equipment
- Multifunction printers
Documentation and Support
Find technical documentation, videos, and training courses for your Arria® V SoC FPGA designs.
Related Links
Related Products
Application Examples
Arria® V SoC FPGA Dev Kit
Documentation
Fundamentals & FAQ