Intel® Stratix® 10 FPGAs and SoCs deliver innovative advantages in performance, power efficiency, density, and system integration. Featuring the revolutionary Intel® Hyperflex™ FPGA Architecture and built combining Intel’s patented Embedded Multi-Die Interconnect Bridge (EMIB) technology, the Advanced Interface Bus (AIB), and a growing portfolio of chiplets, Intel® Stratix® 10 devices deliver up to 2X performance gains over previous-generation, high-performance FPGAs.1
Intel® Stratix® 10 GX FPGAs are designed to meet the high-performance demands of high-throughput systems with up to 10 TFLOPS of floating-point performance and transceiver support up to 28.3 Gbps for chip-module, chip-to-chip, and backplane applications.
Intel® Stratix® 10 SX SoC FPGAs feature hard processor system with 64 bit quad-core ARM* Cortex-A53 processor available in all densities in addition to all the features of Intel® Stratix® 10 GX devices.
Intel® Stratix® 10 TX FPGAs deliver the most advanced transceiver capabilities in the industry by combining H- and E- transceiver tiles. The E-tile provides dual-mode transceiver capabilities, allowing a single transceiver channel to operate up to 56 Gbps in PAM-4 mode or 28.9 Gbps in NRZ mode. Intel® Stratix® 10 TX FPGAs also support the other breakthrough innovations of the Stratix GX and SX variants.
Intel® Stratix® 10 MX FPGAs combine the programmability and flexibility of Intel® Stratix® 10 FPGAs and SoCs with 3D stacked high-bandwidth memory 2 (HBM2) in a single package. Intel® Stratix® 10 MX FPGAs support both H- and E- transceiver tiles.
Intel® Stratix® 10 DX FPGAs are the first FPGA devices to support Intel® Ultra Path Interconnect (Intel® UPI) for direct coherent connection to future select Intel® Xeon® Scalable processor. They include a PCIe* Gen4 interface with up to x16 configuration at 16 GT/s and new memory controller to support select Intel® Optane™ DC persistent memory.
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Intel® Stratix® 10 GX FPGA |
Intel® Stratix® 10 SX SoC FPGA |
Intel® Stratix® 10 TX FPGA |
Intel® Stratix® 10 MX FPGA |
Intel® Stratix® 10 DX |
|---|---|---|---|---|---|
Logic Capacity (KLEs) |
378 - 10,200 |
378 - 2,073 |
378-2,753 |
1,679 – 2,073 |
1,325 – 2,753 |
Arm® Cortex®-A53 HPS |
- |
Yes |
Option |
- |
Option |
| Memory Support | DDR4 / Others |
DDR4 / Others |
DDR4 / Others |
DDR4 / Others HBM2 up 16 GB |
DDR4 / Others HBM2 up to 8 GB Intel® Optane® DC persistent memory |
Max Transceiver Data Rate NRZ/PAM4 |
28.3 Gbps/NA |
28.3 Gbps/NA |
28.9 Gbps/57.8 Gbps |
28.9 Gbps/57.8 Gbps |
28.9 Gbps/57.8 Gbps |
| PCIExpress |
PCIe* Gen3x16 PCIe* Gen4x16* |
PCIe* Gen3x16 PCIe* Gen4x16* |
PCIe* Gen3x16 PCIe* Gen4x16* |
PCIe* Gen3x16 PCIe* Gen4x16* |
PCIe* Gen4x16** |
| UPI | - | - | - | - | Yes |
| *Hard IP support for PCIe* Gen3x16/Soft IP support for PCIe* Gen4x16*; **Hard IP support for PCIe* Gen4x16*. | |||||
Intel® Stratix® 10 devices address the design challenges in next-generation, high-performance systems in wireline and wireless communications, computing, storage, military, broadcast, medical, and test and measurement end markets.
The ground breaking Intel® Hyperflex™ FPGA Architecture delivers up to 2X the core performance.1 With the Intel® Stratix® 10 Families you can extract high levels of performance with up to 8.6 TFLOPS of single-precision floating-point DSP performance and up to twenty 100 GbE interfaces.
Breakthrough Bandwidth Barrier with up to 144 transceivers in a single device, with data rates up to 57.8 Gbps PAM-4 and 28.9 Gbps NRZ. Up to 287.5 Gbps of DDR4 memory bandwidth.Up to 512 Gbps of HBM2 memory bandwidth. PCIExpress hard and soft IP support up to Gen4 x16 at 16 GT/s per lane. Intel® Ultra Path Interconnect (Intel® UPI) hard IP with up to 20 lanes at 11.2 GT/s for direct cache coherent connection to future select Intel® Xeon® Scalable processors.
Achieve Higher System Integration with the largest monolithic FPGA device with 2.8 million LEs and heterogeneous 3D SiP solutions including transceivers and other advanced components such as HBM2. Other system support includes standard external memories and Intel® Optane™ memory products. Intel® Stratix® 10 SoCs come packed with a 64 bit quad-core ARM* Cortex-A53 up to 1.35 GHz with hardened peripherals and high bandwidth interfaces directly to FPGA fabric at 30 Gbps.
Lower Operating Expense by up to 70% lower power than prior-generation high-end FPGAs and SoCs. The Intel® Stratix® 10 devices is optimized for performance with up to 80 Giga floating-point operations per second (GFLOPS)/Watt of single-precision floating point power efficiency.
To address the challenges presented by next-generation systems, Intel® Stratix® 10 FPGAs and SoCs feature the new Intel® Hyperflex™ FPGA Architecture, which delivers 2X the clock frequency performance and up to 70% lower power compared to previous-generation, high-end FPGAs.1
Intel® Stratix® 10 FPGAs and SoCs leverage heterogeneous 3D System-in-Package (SiP) technology to integrate a monolithic FPGA core fabric with 3D SiP transceiver tiles and other advanced components in a single package.
Intel® Stratix® 10 FPGAs and SoCs deliver a new era of transceiver technology with the introduction of innovative heterogeneous 3D System-in-Package (SiP) transceivers.
Intel® Stratix® 10 devices provide memory interface support, including serial, parallel interfaces, and selected Intel® Optane™ DC persistent memory.
The Intel® Stratix® 10 device family introduces a new Secure Device Manager (SDM) available in all densities and device family variants.
With Intel® Stratix® 10 devices, digital signal processing (DSP) designs can achieve up to 8.6 Tera floating point operations per second (TFLOPS) of IEEE 754 single-precision floating-point operations.
Intel® Stratix® 10 DX devices accelerate applications used in Data Center, Networking, Cloud Computing, and Test & Measurement markets through hard and soft intellectual property blocks supporting both UPI and PCIe* Gen4 interfaces.
Building on Intel's leadership in SoCs, Intel® Stratix® 10 SoCs include a next-generation hard processor system (HPS) to deliver the industry's highest performance and most power-efficient SoCs.
Intel® Enpirion® Power Solutions are high-frequency DC-DC step-down power converters designed and validated for Intel® FPGA, CPLD, and SoCs. These robust, easy-to-use power modules integrate nearly all of the components needed to build a power supply – saving you board space and simplifying the design process.
Compatible design tools deliver the highest performance, highest logic utilization, and fastest compile times for high-end FPGA designs.
The Intel® Quartus® Prime Pro Edition Software is optimized to support the advanced features in next-generation FPGAs and SoCs with the Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX device families.
Higher productivity by reducing design partitioning complexity using monolithic FPGA fabric.
fMAX over 900 MHz allows monitoring of all supported protocols at line rates.
UPI for direct coherent connection to future select Intel® Xeon® Scalable processor and PCIe* Gen4 x16 along with Intel® Hyperflex™ FPGA Architecture and configurable DSP engines featuring hardened single-precision FP32 to enable breakthrough in computational throughput.
fMAX over 700 MHz using the Intel® Hyperflex™ FPGA Architecture enabling 400G Ethernet.
Up to 8.6 TFLOPS of IEEE 754 compliant single-precision floating-point performance delivers GPU class performance at a fraction of the power.
Heterogeneous 3D System-in-Package (SiP) integration of transceiver tiles delivers 30G backplane support with a path to 57.8 Gbps and 28.9 Gbps.
Introducing Intel® Stratix® 10 DX FPGA for your high bandwidth and evolving data center requirements. It is the first FPGA to support Intel® Ultra Path Interconnect (Intel® UPI), PCIe* Gen4 x16 and select Intel® Optane™ DC persistent memory DIMMs.
Join Intel Engineers in the lab to learn more about the three main new features in the Intel® Stratix® 10 DX FPGAs: Intel® Ultra Path Interconnect (Intel® UPI), PCIe Gen4 x16 and Intel® Optane™ DC persistent memory DIMMs.
Applications needing massive I/O throughput such as Muxponder and Transponder systems, Optical Switches, and 5G networks need the performance of 58G PAM-4 transceiver I/O's, offered in Intel® Stratix® 10 TX FPGAs.
Intel® Stratix® 10 devices, which include PCIe* and memory controller hard IP blocks, when combined with Avalon® Memory Mapped and direct memory access functions, create a high-performance reference design.
Find technical documentation, videos, and training courses for your Intel® Stratix® 10 device.
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Comparison based on Stratix® V vs. Intel® Stratix® 10 using Intel® Quartus® Prime Pro 16.1 Early Beta. Stratix® V Designs were optimized using 3 step optimization process of Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization in order to utilize Intel® Stratix® 10 architecture enhancements of distributed registers in core fabric. Designs were analyzed using Intel® Quartus® Prime Pro Fast Forward Compile performance exploration tool. For more details, refer to Intel® Hyperflex™ FPGA Architecture Overview White Paper: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01220-hyperflex-architecture-fpga-socs.pdf. Actual performance users will achieve varies based on level of design optimization applied. Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com.au/benchmarks.