Serial Lite III Streaming Intel® FPGA IP
The Serial Lite III Streaming Intel® FPGA Intellectual Property (IP) core offers simple connectivity that enables rapid point-to-point data transfers across various transmission media, including printed circuit board (PCB), backplane, copper cabling, and fiber optics.
Read the Serial Lite III Streaming Intel® FPGA IP user guide ›
Read the Serial Lite III Streaming Intel® Stratix® 10 FPGA IP design example user guide ›
Read the Serial Lite III Streaming Intel® Arria® 10 FPGA IP design example user guide ›
Read the Serial Lite III Streaming Stratix® V FPGA IP design example user guide ›
Serial Lite III Streaming Intel® FPGA IP
Serial Lite III is a simple, low-latency, scalable protocol for high-bandwidth serial data transfer applications.
The Serial Lite III Streaming Intel® FPGA IP core includes Intel’s technology-leading transceivers:
- Physical medium attachment (PMA)
- Physical coding sublayer (PCS)
- Media access control (MAC) layers
The PCS and PMA layers are hardened within the Intel Stratix® 10, Intel Arria® 10, Stratix® V, and Arria® V FPGAs to save customers valuable FPGA logic resources.
Features
The hardened PCS/PMA functionality enables much easier timing closure for all types of designs. The Serial Lite III protocol was designed to provide the necessary reliability, low latency, overhead, and scalability to ensure efficient data transfers and maintain low bit error rates required by today’s and next-generation systems.
- Data rate selection up to 28 Gbps
- Multi-lane configuration up to 24 lanes
- Data streaming operations - continuous or bursty
- Simplex and full duplex operations
- Flexible user clocking modes
- Hardened resource utilization advantage
- Low-latency data transfer (< 150 ns: TX + RX)
- Minimal transmission overhead
- 64B/67B encoding/decoding scheme
- Optional error correction code (ECC) support on M20K's (SEU mitigation)
- Optional error injection or detection and health monitoring
- Fully integrated IP (MAC, PCS, and PMA layers)
- Tunable pre-emphasis and equalization settings
- Support for both AC and DC coupling
Performance and Productivity You Can Expect
Performance |
Productivity |
|---|---|
High data rate efficiency |
Adequate IP timing margin to accelerate full design timing closure |
Over 300 Gbps of aggregate bandwidth for current and emerging applications (up to 24 lanes) |
Intel FPGA IP Evaluation Mode feature allows you to test drive IP for free and without a license |
Low-latency data transfers (< 150 ns: TX + RX) |
Fully integrated Serial Lite III IP includes MAC, PCS, and PMA layers for ease of Intel FPGA IP integration |
AC and DC coupling allows flexibility to tune lane(s) for improved bit error rates |
IP Quality Metrics
Basics |
|
|---|---|
Year IP was first released |
2013 |
Latest version of the Intel Quartus Prime Software supported |
22.2 |
Status |
Production |
Deliverables |
|
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim* - Intel FPGA Edition Timing and/or layout constraints Documentation with revision control Readme file |
Y for all, except for providing Readme file |
Any additional customer deliverables provided with IP |
Testbench and design examples |
Parameterization GUI allowing end user to configure IP |
Y |
IP is enabled for Intel FPGA IP Evaluation Mode Support |
Y |
Source language |
Verilog and VHDL |
Testbench language |
Verilog |
Software drivers provided |
N |
Driver OS Support |
N |
Implementation |
|
User interface |
Avalon Streaming |
IP-XACT metadata |
N |
Verification |
|
Simulators supported |
NCSim, ModelSim, VCS/VCSMX |
Hardware validated |
Intel Arria 10 FPGA Transceiver Signal Integrity Development Kit, Intel Stratix 10 FPGA Signal Integrity Development Kit |
Industry-standard compliance testing performed |
N |
If Yes, which test(s)? |
N/A |
If Yes, on which Intel FPGA device (s)? |
N/A |
If Yes, date performed |
N/A |
If No, is it planned? |
N |
Interoperability |
|
IP has undergone interoperability testing |
Y |
If yes, on which Intel FPGA device(s) |
Intel Stratix 10, Stratix V, Intel Arria 10 GX |
Interoperability reports available |
N |
Automated Generation of Signal Tap II Files for Intel Arria® 10 IP Core Debug
Push-Button Hardware Design Examples in Intel Quartus Prime Software
Related Links
Documentation
- Serial Lite III Streaming Intel® FPGA IP function clocking guidelines for Intel Arria® 10 and V Series Intel® FPGAs ›
(To access this document, contact your local Intel® FPGA sales representative)
- Serial Lite III Streaming Intel® FPGA IP function data efficiency calculator for Intel Arria® 10 and V Series Intel® FPGAs ›
(To access this document, contact your local Intel® FPGA sales representative)
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